3 DECLARE_GLOBAL_DATA_PTR;
5 #define PIN_REG_SIMDA3 (0x8C000470)
6 #define PIN_REG_SIMRST3 (0x8C000478)
7 #define PIN_CTRL_REG (0x8b000028)
9 extern void sprd_gpio_init(void);
10 extern void ADI_init (void);
11 extern int LDO_Init(void);
13 #include <asm/arch/regs_ana.h>
14 #include <asm/arch/adi_hal_internal.h>
16 #define mdelay(n) udelay((n) * 1000)
18 void modem_poweron(void)
22 __raw_writel(0x31,0x8C0003b8);
23 gpio_direction_output(106,1);
24 gpio_set_value(106,1);
26 void modem_poweroff(void)
29 __raw_writel(0x31,0x8C0003b8);
30 gpio_direction_output(106,1);
31 gpio_set_value(106,0);
33 /*Modem download pin,set to high,Modem can not enter downnload mode*/
34 __raw_writel(0x31,0x8C000114);
35 gpio_direction_output(34,1);
39 void Init_7702_modem(void)
42 __raw_writel(0x31,0x8C0003b8);
43 gpio_direction_output(106,1);
44 gpio_set_value(106,0);
45 /*Modem AP_CP Rst pin set to low (default)*/
46 __raw_writel(0x31,0x8C000124);
47 gpio_direction_output(38,1);
51 /*Modem download pin,set to high,Modem can not enter downnload mode*/
52 __raw_writel(0x31,0x8C000114);
53 gpio_direction_output(34,1);
56 __raw_writel(0x31,0x8C0003b8);
57 gpio_direction_output(106,1);
58 gpio_set_value(106,1);
60 __raw_writel(0x174, 0x8C000398);
61 gpio_direction_output(CP_AP_LIV, 0);
62 //gpio_set_value(CP_AP_LIV, 0);
66 void init_calibration_gpio(void)
68 __raw_writel(0x134, 0x8C000430);
69 gpio_direction_output(AP_CP_RTS, 1);
70 gpio_set_value(AP_CP_RTS, 0);
72 __raw_writel(0x1B4, 0x8C000424);
73 gpio_direction_output(CP_AP_RDY, 0);
74 //gpio_set_value(CP_AP_RDY, 0);
76 __raw_writel(0x1B0, 0x8C00039c);
77 gpio_direction_output(CP_AP_RTS, 0);
78 //gpio_set_value(CP_AP_RTS, 0);
80 __raw_writel(0x134, 0x8C000304);
81 gpio_direction_output(AP_CP_RDY, 1);
82 gpio_set_value(AP_CP_RDY, 1);
84 __raw_writel(0x174, 0x8C000398);
85 gpio_direction_output(CP_AP_LIV, 0);
86 //gpio_set_value(CP_AP_LIV, 0);
89 void init_calibration_mode(void)
91 *(volatile unsigned long *)PIN_REG_SIMDA3 |= 0x000003a0;
92 *(volatile unsigned long *)PIN_REG_SIMRST3 |= 0x000003a0;
93 *(volatile unsigned long *)PIN_CTRL_REG |= 0x00000040;
95 init_calibration_gpio();
98 #define PIN_CTL_REG 0x8C000000
99 static void chip_init(void)
101 //ANA_REG_SET(ANA_ADIE_CHIP_ID,0);
102 /* setup pins configration when LDO shutdown*/
103 //__raw_writel(0x1fff00, PIN_CTL_REG);
104 *(volatile unsigned int *)PIN_CTL_REG = 0x1fff00;
108 gd->bd->bi_arch_number = MACH_TYPE_OPENPHONE;
109 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
124 gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1,