1 #include <asm/arch/sci_types.h>
2 #include <asm/arch/adi_hal_internal.h>
3 #include <asm/arch/chip_drv_common_io.h>
4 #include <asm/arch/sprd_reg.h>
6 /***************************************************************************************************************************/
7 /* VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
8 /* AP x x v v v v v v v v v x v v v v v v v */
9 /* CP0 x x v v v x x x x v x x x x x x x x x */
10 /* CP1 x x v x x x x x x x x x x x x x x x x */
11 /* CP2 x x v v x v x x x v x x x x x x x x x */
12 /* EX0 x x x v x x x x x x x x x x x x x x x */
13 /* EX1 x x x x v x x x x x x x x x x x x x x */
14 /* EX2 x x x v x x x x x x x x x x x x x x x */
15 /***************************************************************************************************************************/
17 /***************************************************************************************************************************/
18 /* CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA LPGEN LPARM LPMEM LPCORE LPBG BG */
19 /* AP v v v v v v v v v v v x v v v v v v */
20 /* CP0 x x x x x x x x x x x x x x x x x x */
21 /* CP1 x x x x x x x x x x x x x x x x x x */
22 /* CP2 x x x x x x v v x x x x x x x x x x */
23 /* EX0 x x x x x x x x v x x x x x x x x x */
24 /* EX1 x x x x x x x x x x x x x x x x x x */
25 /* EX2 x x x x x x x x x x x x x x x x x x */
26 /***************************************************************************************************************************/
27 void init_ldo_sleep_gr(void)
30 #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723)
31 ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,
32 BITS_PWR_WR_PROT_VALUE(0x6e7f) |
36 while((ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & BIT_PWR_WR_PROT) != BIT_PWR_WR_PROT);
38 ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
40 BIT_DCDC_TOPCLK6M_PD |
47 //BIT_LDO_EMMCCORE_PD |
58 ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,
59 BITS_PWR_WR_PROT_VALUE(0x0000) |
63 ANA_REG_SET(ANA_REG_GLB_LDO_PD_CTRL,
81 reg_val = ANA_REG_GET(ANA_REG_GLB_LDO_SHPT_PD1);
83 ANA_REG_SET(ANA_REG_GLB_LDO_SHPT_PD1,reg_val);
85 reg_val = ANA_REG_GET(ANA_REG_GLB_LDO_SHPT_PD2);
87 ANA_REG_SET(ANA_REG_GLB_LDO_SHPT_PD2,reg_val);
89 //vddrf 1.5 -> 1.8v for 3532 bug fix
90 ANA_REG_SET(ANA_REG_GLB_DCDC_RF_ADI, 0x180);
92 /* 850/900 swtich module, need open kpled. */
93 ANA_REG_SET(ANA_REG_GLB_KPLED_CTRL, 0xca0);
95 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
97 BIT_SLP_DCDCRF_PD_EN |
98 BIT_SLP_DCDCCON_PD_EN |
99 //BIT_SLP_DCDCGEN_PD_EN |
100 //BIT_SLP_DCDCWPA_PD_EN |
101 BIT_SLP_DCDCARM_PD_EN |
102 BIT_SLP_LDOVDD25_PD_EN |
103 BIT_SLP_LDORF0_PD_EN |
104 BIT_SLP_LDOEMMCCORE_PD_EN |
105 BIT_SLP_LDOGEN0_PD_EN |
106 BIT_SLP_LDODCXO_PD_EN |
107 BIT_SLP_LDOGEN1_PD_EN |
108 BIT_SLP_LDOWIFIPA_PD_EN |
109 //BIT_SLP_LDOVDD28_PD_EN |
110 //BIT_SLP_LDOVDD18_PD_EN |
113 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
115 BIT_SLP_LDOLPREF_PD_EN |
116 BIT_SLP_LDOSDCORE_PD_EN |
117 BIT_SLP_LDOUSB_PD_EN |
118 BIT_SLP_LDOCAMMOT_PD_EN |
119 BIT_SLP_LDOCAMIO_PD_EN |
120 //BIT_SLP_LDOCAMD_PD_EN |
121 BIT_SLP_LDOCAMA_PD_EN |
122 //BIT_SLP_LDOSIM2_PD_EN |
123 //BIT_SLP_LDOSIM1_PD_EN |
124 //BIT_SLP_LDOSIM0_PD_EN |
125 BIT_SLP_LDOSDIO_PD_EN |
128 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
129 //BIT_SLP_DCDCRF_LP_EN |
130 //BIT_SLP_DCDCCON_LP_EN |
131 BIT_SLP_DCDCCORE_LP_EN |
132 BIT_SLP_DCDCMEM_LP_EN |
133 //BIT_SLP_DCDCARM_LP_EN |
134 BIT_SLP_DCDCGEN_LP_EN |
135 //BIT_SLP_DCDCWPA_LP_EN |
136 //BIT_SLP_LDORF0_LP_EN |
137 //BIT_SLP_LDOEMMCCORE_LP_EN |
138 //BIT_SLP_LDOGEN0_LP_EN |
139 //BIT_SLP_LDODCXO_LP_EN |
140 //BIT_SLP_LDOGEN1_LP_EN |
141 //BIT_SLP_LDOWIFIPA_LP_EN |
142 //BIT_SLP_LDOVDD28_LP_EN |
143 //BIT_SLP_LDOVDD18_LP_EN |
146 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
148 //BIT_LDOVDD25_LP_EN_SW |
149 //BIT_LDOSDCORE_LP_EN_SW |
150 //BIT_LDOUSB_LP_EN_SW |
151 //BIT_SLP_LDOVDD25_LP_EN |
152 //BIT_SLP_LDOSDCORE_LP_EN |
153 //BIT_SLP_LDOUSB_LP_EN |
154 //BIT_SLP_LDOCAMMOT_LP_EN |
155 //BIT_SLP_LDOCAMIO_LP_EN |
156 //BIT_SLP_LDOCAMD_LP_EN |
157 //BIT_SLP_LDOCAMA_LP_EN |
158 //BIT_SLP_LDOSIM2_LP_EN |
159 //BIT_SLP_LDOSIM1_LP_EN |
160 //BIT_SLP_LDOSIM0_LP_EN |
161 //BIT_SLP_LDOSDIO_LP_EN |
164 ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL4,
165 //BIT_LDOCAMIO_LP_EN_SW |
166 //BIT_LDOCAMMOT_LP_EN_SW |
167 //BIT_LDOCAMD_LP_EN_SW |
168 //BIT_LDOCAMA_LP_EN_SW |
169 //BIT_LDOSIM2_LP_EN_SW |
170 //BIT_LDOSIM1_LP_EN_SW |
171 //BIT_LDOSIM0_LP_EN_SW |
172 //BIT_LDOSDIO_LP_EN_SW |
173 //BIT_LDORF0_LP_EN_SW |
174 //BIT_LDOEMMCCORE_LP_EN_SW |
175 //BIT_LDOGEN0_LP_EN_SW |
176 //BIT_LDODCXO_LP_EN_SW |
177 //BIT_LDOGEN1_LP_EN_SW |
178 //BIT_LDOWIFIPA_LP_EN_SW |
179 //BIT_LDOVDD28_LP_EN_SW |
180 //BIT_LDOVDD18_LP_EN_SW |
183 ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
184 BIT_SLP_XTLBUF_PD_EN |
186 BITS_XTL_WAIT(0x32) |
190 /****************************************
191 * Following is CP LDO Sleep Control *
192 ****************************************/
193 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
195 //BIT_LDO_GEN0_EXT_XTL0_EN |
196 //BIT_LDO_GEN0_XTL1_EN |
197 BIT_LDO_GEN0_XTL0_EN |
198 BIT_LDO_GEN1_EXT_XTL0_EN |
199 BIT_LDO_GEN1_XTL1_EN |
200 BIT_LDO_GEN1_XTL0_EN |
201 BIT_LDO_DCXO_EXT_XTL0_EN |
202 BIT_LDO_DCXO_XTL1_EN |
203 BIT_LDO_DCXO_XTL0_EN |
204 //BIT_LDO_VDD18_EXT_XTL0_EN |
205 //BIT_LDO_VDD18_XTL1_EN |
206 //BIT_LDO_VDD18_XTL0_EN |
207 //BIT_LDO_VDD28_EXT_XTL0_EN |
208 //BIT_LDO_VDD28_XTL1_EN |
209 //BIT_LDO_VDD28_XTL0_EN |
212 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
213 BIT_LDO_RF0_EXT_XTL0_EN |
214 BIT_LDO_RF0_XTL1_EN |
215 BIT_LDO_RF0_XTL0_EN |
216 BIT_LDO_WIFIPA_EXT_XTL0_EN |
217 //BIT_LDO_WIFIPA_XTL1_EN |
218 //BIT_LDO_WIFIPA_XTL0_EN |
219 //BIT_LDO_SIM2_EXT_XTL0_EN |
220 //BIT_LDO_SIM2_XTL1_EN |
221 //BIT_LDO_SIM2_XTL0_EN |
222 //BIT_LDO_SIM1_EXT_XTL0_EN |
223 //BIT_LDO_SIM1_XTL1_EN |
224 //BIT_LDO_SIM1_XTL0_EN |
225 //BIT_LDO_SIM0_EXT_XTL0_EN |
226 //BIT_LDO_SIM0_XTL1_EN |
227 //BIT_LDO_SIM0_XTL0_EN |
230 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
231 BIT_LDO_VDD25_EXT_XTL0_EN |
232 BIT_LDO_VDD25_XTL1_EN |
233 BIT_LDO_VDD25_XTL0_EN |
234 BIT_DCDC_RF_EXT_XTL0_EN |
235 BIT_DCDC_RF_XTL1_EN |
236 BIT_DCDC_RF_XTL0_EN |
245 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
246 BIT_DCDC_CON_EXT_XTL0_EN |
247 BIT_DCDC_CON_XTL1_EN |
248 BIT_DCDC_CON_XTL0_EN |
249 //BIT_DCDC_WPA_EXT_XTL0_EN |
250 BIT_DCDC_WPA_XTL1_EN |
251 //BIT_DCDC_WPA_XTL0_EN |
252 BIT_DCDC_MEM_EXT_XTL0_EN |
253 BIT_DCDC_MEM_XTL1_EN |
254 BIT_DCDC_MEM_XTL0_EN |
255 BIT_DCDC_GEN_EXT_XTL0_EN |
256 BIT_DCDC_GEN_XTL1_EN |
257 BIT_DCDC_GEN_XTL0_EN |
258 BIT_DCDC_CORE_EXT_XTL0_EN |
259 BIT_DCDC_CORE_XTL1_EN |
260 BIT_DCDC_CORE_XTL0_EN |
264 //bit4-5: 0x10. quick dischrg
265 reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_DISCHRG);
266 reg_val |= (0x1 << 5);
267 reg_val &= 0xFFFFFFEF;
268 ANA_REG_SET(ANA_REG_GLB_DCDC_DISCHRG, reg_val);
271 ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCCLR,
272 //BIT_LDO_AVDD18_PD_RTCCLR |
273 BIT_DCDC_OTP_PD_RTCCLR |
274 //BIT_DCDC_WRF_PD_RTCCLR |
275 BIT_DCDC_GEN_PD_RTCCLR |
276 BIT_DCDC_MEM_PD_RTCCLR |
277 BIT_DCDC_ARM_PD_RTCCLR |
278 BIT_DCDC_CORE_PD_RTCCLR|
279 BIT_LDO_EMMCCORE_PD_RTCCLR |
280 BIT_LDO_EMMCIO_PD_RTCCLR |
281 BIT_LDO_RF2_PD_RTCCLR |
282 //BIT_LDO_RF1_PD_RTCCLR |
283 BIT_LDO_RF0_PD_RTCCLR |
284 BIT_LDO_VDD25_PD_RTCCLR |
285 BIT_LDO_VDD28_PD_RTCCLR |
286 BIT_LDO_VDD18_PD_RTCCLR |
291 ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCSET,
292 BIT_LDO_AVDD18_PD_RTCSET |
293 //BIT_DCDC_OTP_PD_RTCSET |
294 BIT_DCDC_WRF_PD_RTCSET |
295 //BIT_DCDC_GEN_PD_RTCSET |
296 //BIT_DCDC_MEM_PD_RTCSET |
297 //BIT_DCDC_ARM_PD_RTCSET |
298 //BIT_DCDC_CORE_PD_RTCSET|
299 //BIT_LDO_EMMCCORE_PD_RTCSET |
300 //BIT_LDO_EMMCIO_PD_RTCSET |
301 //BIT_LDO_RF2_PD_RTCSET |
302 BIT_LDO_RF1_PD_RTCSET |
303 //BIT_LDO_RF0_PD_RTCSET |
304 //BIT_LDO_VDD25_PD_RTCSET |
305 //BIT_LDO_VDD28_PD_RTCSET |
306 //BIT_LDO_VDD18_PD_RTCSET |
311 /**********************************************
312 * Following is AP LDO A DIE Sleep Control *
313 *********************************************/
314 ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL0,
316 BIT_SLP_DCDC_OTP_PD_EN |
317 //BIT_SLP_DCDCGEN_PD_EN |
318 //BIT_SLP_DCDCWPA_PD_EN |
319 //BIT_SLP_DCDCWRF_PD_EN |
320 BIT_SLP_DCDCARM_PD_EN |
321 BIT_SLP_LDOEMMCCORE_PD_EN |
322 BIT_SLP_LDOEMMCIO_PD_EN |
323 BIT_SLP_LDORF2_PD_EN |
324 //BIT_SLP_LDORF1_PD_EN |
325 BIT_SLP_LDORF0_PD_EN |
326 BIT_SLP_LDOVDD25_PD_EN |
327 //BIT_SLP_LDOVDD28_PD_EN |
328 //BIT_SLP_LDOVDD18_PD_EN |
332 ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL1,
334 BIT_SLP_LDOLPREF_PD_EN |
335 BIT_SLP_LDOCLSG_PD_EN |
336 BIT_SLP_LDOUSB_PD_EN |
337 BIT_SLP_LDOCAMMOT_PD_EN |
338 BIT_SLP_LDOCAMIO_PD_EN |
339 BIT_SLP_LDOCAMD_PD_EN |
340 BIT_SLP_LDOCAMA_PD_EN |
341 //BIT_SLP_LDOSIM2_PD_EN |
342 //BIT_SLP_LDOSIM1_PD_EN |
343 //BIT_SLP_LDOSIM0_PD_EN |
344 BIT_SLP_LDOSD_PD_EN |
345 BIT_SLP_LDOAVDD18_PD_EN |
349 ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL2,
350 //BIT_SLP_DCDC_BG_LP_EN |
351 //BIT_SLP_DCDCCORE_LP_EN |
352 //BIT_SLP_DCDCMEM_LP_EN |
353 //BIT_SLP_DCDCARM_LP_EN |
354 //BIT_SLP_DCDCGEN_LP_EN |
355 //BIT_SLP_DCDCWPA_LP_EN |
356 //BIT_SLP_DCDCWRF_LP_EN |
357 //BIT_SLP_LDOEMMCCORE_LP_EN |
358 //BIT_SLP_LDOEMMCIO_LP_EN |
359 //BIT_SLP_LDORF2_LP_EN |
360 //BIT_SLP_LDORF1_LP_EN |
361 //BIT_SLP_LDORF0_LP_EN |
365 ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL3,
367 //BIT_SLP_LDOVDD25_LP_EN |
368 //BIT_SLP_LDOVDD28_LP_EN |
369 //BIT_SLP_LDOVDD18_LP_EN |
370 //BIT_SLP_LDOCLSG_LP_EN |
371 //BIT_SLP_LDOUSB_LP_EN |
372 //BIT_SLP_LDOCAMMOT_LP_EN |
373 //BIT_SLP_LDOCAMIO_LP_EN |
374 //BIT_SLP_LDOCAMD_LP_EN |
375 //BIT_SLP_LDOCAMA_LP_EN |
376 //BIT_SLP_LDOSIM2_LP_EN |
377 //BIT_SLP_LDOSIM1_LP_EN |
378 //BIT_SLP_LDOSIM0_LP_EN |
379 //BIT_SLP_LDOSD_LP_EN |
380 //BIT_SLP_LDOAVDD18_LP_EN |
384 ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
385 BIT_SLP_XTLBUF_PD_EN |
391 ANA_REG_SET(ANA_REG_GLB_DDR2_CTRL,
393 BITS_DDR2_BUF_S_DS(0x0) |
394 BITS_DDR2_BUF_CHNS_DS(0x0) |
396 BITS_DDR2_BUF_S(0x3) |
397 BITS_DDR2_BUF_CHNS(0x0) |
401 /****************************************
402 * Following is CP LDO Sleep Control *
403 ****************************************/
405 ANA_REG_SET(ANA_REG_GLB_LDO1828_XTL_CTL,
406 //BIT_LDO_VDD18_EXT_XTL2_EN |
407 //BIT_LDO_VDD18_EXT_XTL1_EN |
408 //BIT_LDO_VDD18_EXT_XTL0_EN |
409 //BIT_LDO_VDD18_XTL2_EN |
410 //BIT_LDO_VDD18_XTL1_EN |
411 //BIT_LDO_VDD18_XTL0_EN |
412 //BIT_LDO_VDD28_EXT_XTL2_EN |
413 //BIT_LDO_VDD28_EXT_XTL1_EN |
414 //BIT_LDO_VDD28_EXT_XTL0_EN |
415 //BIT_LDO_VDD28_XTL2_EN |
416 //BIT_LDO_VDD28_XTL1_EN |
417 //BIT_LDO_VDD28_XTL0_EN |
421 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
423 //BIT_LDO_RF1_EXT_XTL2_EN |
424 //BIT_LDO_RF1_EXT_XTL1_EN |
425 //BIT_LDO_RF1_EXT_XTL0_EN |
426 //BIT_LDO_RF1_XTL2_EN |
427 //BIT_LDO_RF1_XTL1_EN |
428 //BIT_LDO_RF1_XTL0_EN |
429 //BIT_LDO_RF0_EXT_XTL2_EN |
430 //BIT_LDO_RF0_EXT_XTL1_EN |
431 //BIT_LDO_RF0_EXT_XTL0_EN |
432 BIT_LDO_RF0_XTL2_EN |
433 BIT_LDO_RF0_XTL1_EN |
434 BIT_LDO_RF0_XTL0_EN |
438 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
439 //BIT_LDO_VDD25_EXT_XTL2_EN |
440 //BIT_LDO_VDD25_EXT_XTL1_EN |
441 //BIT_LDO_VDD25_EXT_XTL0_EN |
442 BIT_LDO_VDD25_XTL2_EN |
443 BIT_LDO_VDD25_XTL1_EN |
444 BIT_LDO_VDD25_XTL0_EN |
445 //BIT_LDO_RF2_EXT_XTL2_EN |
446 //BIT_LDO_RF2_EXT_XTL1_EN |
447 //BIT_LDO_RF2_EXT_XTL0_EN |
448 BIT_LDO_RF2_XTL2_EN |
449 BIT_LDO_RF2_XTL1_EN |
450 BIT_LDO_RF2_XTL0_EN |
454 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
455 //BIT_LDO_AVDD18_EXT_XTL2_EN |
456 //BIT_LDO_AVDD18_EXT_XTL1_EN |
457 //BIT_LDO_AVDD18_EXT_XTL0_EN |
458 //BIT_LDO_AVDD18_XTL2_EN |
459 //BIT_LDO_AVDD18_XTL1_EN |
460 //BIT_LDO_AVDD18_XTL0_EN |
461 //BIT_LDO_SIM2_EXT_XTL2_EN |
462 //BIT_LDO_SIM2_EXT_XTL1_EN |
463 //BIT_LDO_SIM2_EXT_XTL0_EN |
464 //BIT_LDO_SIM2_XTL2_EN |
465 //BIT_LDO_SIM2_XTL1_EN |
466 //BIT_LDO_SIM2_XTL0_EN |
470 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
471 //BIT_DCDC_BG_EXT_XTL2_EN |
472 //BIT_DCDC_BG_EXT_XTL1_EN |
473 //BIT_DCDC_BG_EXT_XTL0_EN |
474 BIT_DCDC_BG_XTL2_EN |
475 BIT_DCDC_BG_XTL1_EN |
476 BIT_DCDC_BG_XTL0_EN |
477 //BIT_BG_EXT_XTL2_EN |
478 //BIT_BG_EXT_XTL1_EN |
479 //BIT_BG_EXT_XTL0_EN |
486 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
487 //BIT_DCDC_WRF_XTL2_EN |
488 //BIT_DCDC_WRF_XTL1_EN |
489 //BIT_DCDC_WRF_XTL0_EN |
490 BIT_DCDC_WPA_XTL2_EN |
491 //BIT_DCDC_WPA_XTL1_EN |
492 //BIT_DCDC_WPA_XTL0_EN |
493 BIT_DCDC_MEM_XTL2_EN |
494 BIT_DCDC_MEM_XTL1_EN |
495 BIT_DCDC_MEM_XTL0_EN |
496 BIT_DCDC_GEN_XTL2_EN |
497 BIT_DCDC_GEN_XTL1_EN |
498 BIT_DCDC_GEN_XTL0_EN |
499 BIT_DCDC_CORE_XTL2_EN |
500 BIT_DCDC_CORE_XTL1_EN |
501 BIT_DCDC_CORE_XTL0_EN |
505 ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN5,
506 //BIT_DCDC_WRF_EXT_XTL2_EN |
507 //BIT_DCDC_WRF_EXT_XTL1_EN |
508 //BIT_DCDC_WRF_EXT_XTL0_EN |
509 //BIT_DCDC_WPA_EXT_XTL2_EN |
510 //BIT_DCDC_WPA_EXT_XTL1_EN |
511 //BIT_DCDC_WPA_EXT_XTL0_EN |
512 //BIT_DCDC_MEM_EXT_XTL2_EN |
513 //BIT_DCDC_MEM_EXT_XTL1_EN |
514 //BIT_DCDC_MEM_EXT_XTL0_EN |
515 //BIT_DCDC_GEN_EXT_XTL2_EN |
516 //BIT_DCDC_GEN_EXT_XTL1_EN |
517 //BIT_DCDC_GEN_EXT_XTL0_EN |
518 //BIT_DCDC_CORE_EXT_XTL2_EN |
519 //BIT_DCDC_CORE_EXT_XTL1_EN |
520 //BIT_DCDC_CORE_EXT_XTL0_EN |
525 /************************************************
526 * Following is AP/CP LDO D DIE Sleep Control *
527 *************************************************/
529 CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
537 CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
545 CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
553 CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
554 BIT_XTLBUF0_CP2_SEL |
555 BIT_XTLBUF0_CP1_SEL |
556 BIT_XTLBUF0_CP0_SEL |
561 CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
562 BIT_XTLBUF1_CP2_SEL |
563 BIT_XTLBUF1_CP1_SEL |
564 BIT_XTLBUF1_CP0_SEL |
569 CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
578 CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
586 /*caution tdpll & wpll sel config in spl*/
587 reg_val = CHIP_REG_GET(REG_PMU_APB_TDPLL_REL_CFG);
595 CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,reg_val);
597 reg_val = CHIP_REG_GET(REG_PMU_APB_WPLL_REL_CFG);
605 CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,reg_val);
607 CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
616 CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG,
617 BIT_WIFIPLL1_REF_SEL |
618 BIT_WIFIPLL1_CP2_SEL |
619 //BIT_WIFIPLL1_CP1_SEL |
620 //BIT_WIFIPLL1_CP0_SEL |
621 //BIT_WIFIPLL1_AP_SEL |
625 CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG,
626 BIT_WIFIPLL2_REF_SEL |
627 BIT_WIFIPLL2_CP2_SEL |
628 //BIT_WIFIPLL2_CP1_SEL |
629 //BIT_WIFIPLL2_CP0_SEL |
630 //BIT_WIFIPLL2_AP_SEL |
634 CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
635 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN |
636 BITS_PD_CA7_TOP_PWR_ON_DLY(8) |
637 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2) |
638 BITS_PD_CA7_TOP_ISO_ON_DLY(4) |
642 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
643 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN |
644 BITS_PD_CA7_C0_PWR_ON_DLY(8) |
645 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6) |
646 BITS_PD_CA7_C0_ISO_ON_DLY(2) |
650 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
651 BIT_PD_CA7_C1_FORCE_SHUTDOWN |
652 BITS_PD_CA7_C1_PWR_ON_DLY(8) |
653 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4) |
654 BITS_PD_CA7_C1_ISO_ON_DLY(2) |
658 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
659 BIT_PD_CA7_C2_FORCE_SHUTDOWN |
660 BITS_PD_CA7_C2_PWR_ON_DLY(8) |
661 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4) |
662 BITS_PD_CA7_C2_ISO_ON_DLY(2) |
666 CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
667 BIT_PD_CA7_C3_FORCE_SHUTDOWN |
668 BITS_PD_CA7_C3_PWR_ON_DLY(8) |
669 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4) |
670 BITS_PD_CA7_C3_ISO_ON_DLY(2) |
674 CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
675 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN |
676 BITS_PD_AP_SYS_PWR_ON_DLY(8) |
677 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0) |
678 BITS_PD_AP_SYS_ISO_ON_DLY(6) |
682 CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
683 BIT_PD_MM_TOP_FORCE_SHUTDOWN |
684 BITS_PD_MM_TOP_PWR_ON_DLY(8) |
685 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0) |
686 BITS_PD_MM_TOP_ISO_ON_DLY(4) |
690 CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
691 BIT_PD_GPU_TOP_FORCE_SHUTDOWN |
692 BITS_PD_GPU_TOP_PWR_ON_DLY(8) |
693 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0) |
694 BITS_PD_GPU_TOP_ISO_ON_DLY(4) |
698 CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
699 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN |
700 BITS_PD_PUB_SYS_PWR_ON_DLY(8) |
701 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0) |
702 BITS_PD_PUB_SYS_ISO_ON_DLY(6) |
706 CHIP_REG_SET(REG_PMU_APB_PD_DDR_PUBL_CFG,
707 BIT_PD_DDR_PUBL_AUTO_SHUTDOWN_EN |
708 BITS_PD_DDR_PUBL_PWR_ON_DLY(8) |
709 BITS_PD_DDR_PUBL_PWR_ON_SEQ_DLY(0) |
710 BITS_PD_DDR_PUBL_ISO_ON_DLY(6) |
714 CHIP_REG_SET(REG_PMU_APB_PD_DDR_PHY_CFG,
715 BIT_PD_DDR_PHY_AUTO_SHUTDOWN_EN |
716 BITS_PD_DDR_PHY_PWR_ON_DLY(8) |
717 BITS_PD_DDR_PHY_PWR_ON_SEQ_DLY(0) |
718 BITS_PD_DDR_PHY_ISO_ON_DLY(6) |
722 CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
723 BITS_XTL1_WAIT_CNT(0x73) |
724 BITS_XTL0_WAIT_CNT(0x73) |
728 CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
729 BITS_XTLBUF1_WAIT_CNT(7) |
730 BITS_XTLBUF0_WAIT_CNT(7) |
734 CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
735 BITS_WPLL_WAIT_CNT(7) |
736 BITS_TDPLL_WAIT_CNT(7) |
737 BITS_DPLL_WAIT_CNT(7) |
738 BITS_MPLL_WAIT_CNT(7) |
742 CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
743 BITS_WIFIPLL2_WAIT_CNT(7) |
744 BITS_WIFIPLL1_WAIT_CNT(7) |
745 BITS_CPLL_WAIT_CNT(7) |
749 ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
750 BITS_SLP_IN_WAIT_DCDCARM(7) |
751 BITS_SLP_OUT_WAIT_DCDCARM(8) |
755 CHIP_REG_SET(REG_PMU_APB_PD_CODEC_TOP_CFG,
756 BIT_PD_CODEC_TOP_AUTO_SHUTDOWN_EN |
757 BITS_PD_CODEC_TOP_PWR_ON_DLY(8) |
758 BITS_PD_CODEC_TOP_PWR_ON_SEQ_DLY(0) |
759 BITS_PD_CODEC_TOP_ISO_ON_DLY(4) |
763 /*chip service package init*/