board/spreadtrum/core3/ldo_sleep.c

   1 #include <asm/arch/sci_types.h>
   2 #include <asm/arch/adi_hal_internal.h>
   3 #include <asm/arch/chip_drv_common_io.h>
   4 #include <asm/arch/sprd_reg.h>
   5
   6 /***************************************************************************************************************************/
   7 /*     VDD18 VDD28 VDD25 RF0 RF1 RF2 EMMCIO EMMCCORE DCDCARM DCDCWRF DCDCWPA DCDCGEN DCDCOTP AVDD18 SD SIM0 SIM1 SIM2 CAMA */
   8 /* AP    x     x    v     v   v   v     v      v        v       v       v       x       v      v    v    v   v     v    v  */
   9 /* CP0   x     x    v     v   v   x     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  10 /* CP1   x     x    v     x   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  11 /* CP2   x     x    v     v   x   v     x      x        x       v       x       x       x      x    x    x   x     x    x  */
  12 /* EX0   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  13 /* EX1   x     x    x     x   v   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  14 /* EX2   x     x    x     v   x   x     x      x        x       x       x       x       x      x    x    x   x     x    x  */
  15 /***************************************************************************************************************************/
  16
  17 /***************************************************************************************************************************/
  18 /*     CAMD CMAIO CAMMOT USB CLSG LPREF LPRF0 LPRF1 LPRF2 LPEMMCIO LPEMMCCORE LPWPA  LPGEN   LPARM LPMEM LPCORE LPBG  BG   */
  19 /* AP    v     v    v     v   v   v     v      v     v       v       v          x       v      v     v     v     v     v   */
  20 /* CP0   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  21 /* CP1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  22 /* CP2   x     x    x     x   x   x     v      v     x       x       x          x       x      x     x     x     x     x   */
  23 /* EX0   x     x    x     x   x   x     x      x     v       x       x          x       x      x     x     x     x     x   */
  24 /* EX1   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  25 /* EX2   x     x    x     x   x   x     x      x     x       x       x          x       x      x     x     x     x     x   */
  26 /***************************************************************************************************************************/
  27 void init_ldo_sleep_gr(void)
  28 {
  29         unsigned int reg_val;
  30 #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723)
  31         ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,
  32                 BITS_PWR_WR_PROT_VALUE(0x5e6f) |
  33                 0
  34         );
  35
  36         while((ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & BIT_PWR_WR_PROT) == BIT_PWR_WR_PROT);
  37
  38         ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
  39                 BIT_LDO_EMM_PD |
  40                 //BIT_DCDC_TOPCLK6M_PD |
  41                 //BIT_DCDC_RF_PD |
  42                 //BIT_DCDC_GEN_PD |
  43                 //BIT_DCDC_MEM_PD |
  44                 //BIT_DCDC_ARM_PD |
  45                 //BIT_DCDC_CORE_PD |
  46                 //BIT_LDO_RF0_PD |
  47                 //BIT_LDO_EMMCCORE_PD |
  48                 //BIT_LDO_GEN1_PD |
  49                 //BIT_LDO_DCXO_PD |
  50                 //BIT_LDO_GEN0_PD |
  51                 //BIT_LDO_VDD25_PD |
  52                 //BIT_LDO_VDD28_PD |
  53                 //BIT_LDO_VDD18_PD |
  54                 //BIT_BG_PD |
  55                 0
  56         );
  57
  58         ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,
  59                 BITS_PWR_WR_PROT_VALUE(0x0000) |
  60                 0
  61         );
  62
  63         ANA_REG_SET(ANA_REG_GLB_LDO_PD_CTRL,
  64                 BIT_LDO_LPREF_PD_SW |
  65                 BIT_DCDC_WPA_PD |
  66                 BIT_DCDC_CON_PD |
  67                 BIT_LDO_WIFIPA_PD |
  68                 BIT_LDO_SDCORE_PD |
  69                 BIT_LDO_USB_PD |
  70                 BIT_LDO_CAMMOT_PD |
  71                 BIT_LDO_CAMIO_PD |
  72                 BIT_LDO_CAMD_PD |
  73                 BIT_LDO_CAMA_PD |
  74                 BIT_LDO_SIM2_PD |
  75                 //BIT_LDO_SIM1_PD |
  76                 //BIT_LDO_SIM0_PD |
  77                 //BIT_LDO_SDIO_PD |
  78                 0
  79         );
  80         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
  81                 BIT_SLP_IO_EN |
  82                 BIT_SLP_DCDCRF_PD_EN |
  83                 BIT_SLP_DCDCCON_PD_EN |
  84                 //BIT_SLP_DCDCGEN_PD_EN |
  85                 BIT_SLP_DCDCWPA_PD_EN |
  86                 BIT_SLP_DCDCARM_PD_EN |
  87                 BIT_SLP_LDOVDD25_PD_EN |
  88                 BIT_SLP_LDORF0_PD_EN |
  89                 BIT_SLP_LDOEMMCCORE_PD_EN |
  90                 BIT_SLP_LDOGEN0_PD_EN |
  91                 BIT_SLP_LDODCXO_PD_EN |
  92                 //BIT_SLP_LDOGEN1_PD_EN |
  93                 BIT_SLP_LDOWIFIPA_PD_EN |
  94                 //BIT_SLP_LDOVDD28_PD_EN |
  95                 //BIT_SLP_LDOVDD18_PD_EN |
  96                 0
  97         );
  98         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
  99                 BIT_SLP_LDO_PD_EN |
 100                 BIT_SLP_LDOLPREF_PD_EN |
 101                 BIT_SLP_LDOSDCORE_PD_EN |
 102                 BIT_SLP_LDOUSB_PD_EN |
 103                 BIT_SLP_LDOCAMMOT_PD_EN |
 104                 BIT_SLP_LDOCAMIO_PD_EN |
 105                 BIT_SLP_LDOCAMD_PD_EN |
 106                 BIT_SLP_LDOCAMA_PD_EN |
 107                 BIT_SLP_LDOSIM2_PD_EN |
 108                 //BIT_SLP_LDOSIM1_PD_EN |
 109                 //BIT_SLP_LDOSIM0_PD_EN |
 110                 BIT_SLP_LDOSDIO_PD_EN |
 111                 0
 112         );
 113         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
 114                 //BIT_SLP_DCDCRF_LP_EN |
 115                 //BIT_SLP_DCDCCON_LP_EN |
 116                 //BIT_SLP_DCDCCORE_LP_EN |
 117                 //BIT_SLP_DCDCMEM_LP_EN |
 118                 //BIT_SLP_DCDCARM_LP_EN |
 119                 //BIT_SLP_DCDCGEN_LP_EN |
 120                 //BIT_SLP_DCDCWPA_LP_EN |
 121                 //BIT_SLP_LDORF0_LP_EN |
 122                 //BIT_SLP_LDOEMMCCORE_LP_EN |
 123                 //BIT_SLP_LDOGEN0_LP_EN |
 124                 //BIT_SLP_LDODCXO_LP_EN |
 125                 //BIT_SLP_LDOGEN1_LP_EN |
 126                 //BIT_SLP_LDOWIFIPA_LP_EN |
 127                 //BIT_SLP_LDOVDD28_LP_EN |
 128                 //BIT_SLP_LDOVDD18_LP_EN |
 129                 0
 130         );
 131         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
 132                 //BIT_SLP_BG_LP_EN |
 133                 //BIT_LDOVDD25_LP_EN_SW |
 134                 //BIT_LDOSDCORE_LP_EN_SW |
 135                 //BIT_LDOUSB_LP_EN_SW |
 136                 //BIT_SLP_LDOVDD25_LP_EN |
 137                 //BIT_SLP_LDOSDCORE_LP_EN |
 138                 //BIT_SLP_LDOUSB_LP_EN |
 139                 //BIT_SLP_LDOCAMMOT_LP_EN |
 140                 //BIT_SLP_LDOCAMIO_LP_EN |
 141                 //BIT_SLP_LDOCAMD_LP_EN |
 142                 //BIT_SLP_LDOCAMA_LP_EN |
 143                 //BIT_SLP_LDOSIM2_LP_EN |
 144                 //BIT_SLP_LDOSIM1_LP_EN |
 145                 //BIT_SLP_LDOSIM0_LP_EN |
 146                 //BIT_SLP_LDOSDIO_LP_EN |
 147                 0
 148         );
 149         ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL4,
 150                 //BIT_LDOCAMIO_LP_EN_SW |
 151                 //BIT_LDOCAMMOT_LP_EN_SW |
 152                 //BIT_LDOCAMD_LP_EN_SW |
 153                 //BIT_LDOCAMA_LP_EN_SW |
 154                 //BIT_LDOSIM2_LP_EN_SW |
 155                 //BIT_LDOSIM1_LP_EN_SW |
 156                 //BIT_LDOSIM0_LP_EN_SW |
 157                 //BIT_LDOSDIO_LP_EN_SW |
 158                 //BIT_LDORF0_LP_EN_SW |
 159                 //BIT_LDOEMMCCORE_LP_EN_SW |
 160                 //BIT_LDOGEN0_LP_EN_SW |
 161                 //BIT_LDODCXO_LP_EN_SW |
 162                 //BIT_LDOGEN1_LP_EN_SW |
 163                 //BIT_LDOWIFIPA_LP_EN_SW |
 164                 //BIT_LDOVDD28_LP_EN_SW |
 165                 //BIT_LDOVDD18_LP_EN_SW |
 166                 0
 167         );
 168         ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
 169                 BIT_SLP_XTLBUF_PD_EN |
 170                 BIT_XTL_EN |
 171                 BITS_XTL_WAIT(0x32) |
 172                 0
 173         );
 174
 175         /****************************************
 176         *   Following is CP LDO Sleep Control  *
 177         ****************************************/
 178         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
 179                 BIT_LDO_XTL_EN |
 180                 //BIT_LDO_GEN0_EXT_XTL0_EN |
 181                 //BIT_LDO_GEN0_XTL1_EN |
 182                 BIT_LDO_GEN0_XTL0_EN |
 183                 //BIT_LDO_GEN1_EXT_XTL0_EN |
 184                 //BIT_LDO_GEN1_XTL1_EN |
 185                 //BIT_LDO_GEN1_XTL0_EN |
 186                 BIT_LDO_DCXO_EXT_XTL0_EN |
 187                 BIT_LDO_DCXO_XTL1_EN |
 188                 BIT_LDO_DCXO_XTL0_EN |
 189                 //BIT_LDO_VDD18_EXT_XTL0_EN |
 190                 //BIT_LDO_VDD18_XTL1_EN |
 191                 //BIT_LDO_VDD18_XTL0_EN |
 192                 //BIT_LDO_VDD28_EXT_XTL0_EN |
 193                 //BIT_LDO_VDD28_XTL1_EN |
 194                 //BIT_LDO_VDD28_XTL0_EN |
 195                 0
 196         );
 197         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
 198                 BIT_LDO_RF0_EXT_XTL0_EN |
 199                 BIT_LDO_RF0_XTL1_EN |
 200                 BIT_LDO_RF0_XTL0_EN |
 201                 BIT_LDO_WIFIPA_EXT_XTL0_EN |
 202                 BIT_LDO_WIFIPA_XTL1_EN |
 203                 BIT_LDO_WIFIPA_XTL0_EN |
 204                 //BIT_LDO_SIM2_EXT_XTL0_EN |
 205                 //BIT_LDO_SIM2_XTL1_EN |
 206                 //BIT_LDO_SIM2_XTL0_EN |
 207                 BIT_LDO_SIM1_EXT_XTL0_EN |
 208                 BIT_LDO_SIM1_XTL1_EN |
 209                 BIT_LDO_SIM1_XTL0_EN |
 210                 BIT_LDO_SIM0_EXT_XTL0_EN |
 211                 BIT_LDO_SIM0_XTL1_EN |
 212                 BIT_LDO_SIM0_XTL0_EN |
 213                 0
 214         );
 215         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
 216                 BIT_LDO_VDD25_EXT_XTL0_EN |
 217                 BIT_LDO_VDD25_XTL1_EN |
 218                 BIT_LDO_VDD25_XTL0_EN |
 219                 BIT_DCDC_RF_EXT_XTL0_EN |
 220                 BIT_DCDC_RF_XTL1_EN |
 221                 BIT_DCDC_RF_XTL0_EN |
 222                 BIT_XO_EXT_XTL0_EN |
 223                 BIT_XO_XTL1_EN |
 224                 BIT_XO_XTL0_EN |
 225                 BIT_BG_EXT_XTL0_EN |
 226                 BIT_BG_XTL1_EN |
 227                 BIT_BG_XTL0_EN |
 228                 0
 229         );
 230         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
 231                 BIT_DCDC_CON_EXT_XTL0_EN |
 232                 BIT_DCDC_CON_XTL1_EN |
 233                 BIT_DCDC_CON_XTL0_EN |
 234                 BIT_DCDC_WPA_EXT_XTL0_EN |
 235                 //BIT_DCDC_WPA_XTL1_EN |
 236                 //BIT_DCDC_WPA_XTL0_EN |
 237                 //BIT_DCDC_MEM_EXT_XTL0_EN |
 238                 BIT_DCDC_MEM_XTL1_EN |
 239                 BIT_DCDC_MEM_XTL0_EN |
 240                 BIT_DCDC_GEN_EXT_XTL0_EN |
 241                 BIT_DCDC_GEN_XTL1_EN |
 242                 BIT_DCDC_GEN_XTL0_EN |
 243                 BIT_DCDC_CORE_EXT_XTL0_EN |
 244                 BIT_DCDC_CORE_XTL1_EN |
 245                 BIT_DCDC_CORE_XTL0_EN |
 246                 0
 247         );
 248
 249
 250 #else
 251         ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCCLR,
 252                 //BIT_LDO_AVDD18_PD_RTCCLR |
 253                 BIT_DCDC_OTP_PD_RTCCLR |
 254                 //BIT_DCDC_WRF_PD_RTCCLR |
 255                 BIT_DCDC_GEN_PD_RTCCLR |
 256                 BIT_DCDC_MEM_PD_RTCCLR |
 257                 BIT_DCDC_ARM_PD_RTCCLR |
 258                 BIT_DCDC_CORE_PD_RTCCLR|
 259                 BIT_LDO_EMMCCORE_PD_RTCCLR |
 260                 BIT_LDO_EMMCIO_PD_RTCCLR |
 261                 BIT_LDO_RF2_PD_RTCCLR |
 262                 //BIT_LDO_RF1_PD_RTCCLR |
 263                 BIT_LDO_RF0_PD_RTCCLR |
 264                 BIT_LDO_VDD25_PD_RTCCLR |
 265                 BIT_LDO_VDD28_PD_RTCCLR |
 266                 BIT_LDO_VDD18_PD_RTCCLR |
 267                 BIT_BG_PD_RTCCLR |
 268                 0
 269         );
 270
 271         ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCSET,
 272                 BIT_LDO_AVDD18_PD_RTCSET |
 273                 //BIT_DCDC_OTP_PD_RTCSET |
 274                 BIT_DCDC_WRF_PD_RTCSET |
 275                 //BIT_DCDC_GEN_PD_RTCSET |
 276                 //BIT_DCDC_MEM_PD_RTCSET |
 277                 //BIT_DCDC_ARM_PD_RTCSET |
 278                 //BIT_DCDC_CORE_PD_RTCSET|
 279                 //BIT_LDO_EMMCCORE_PD_RTCSET |
 280                 //BIT_LDO_EMMCIO_PD_RTCSET |
 281                 //BIT_LDO_RF2_PD_RTCSET |
 282                 BIT_LDO_RF1_PD_RTCSET |
 283                 //BIT_LDO_RF0_PD_RTCSET |
 284                 //BIT_LDO_VDD25_PD_RTCSET |
 285                 //BIT_LDO_VDD28_PD_RTCSET |
 286                 //BIT_LDO_VDD18_PD_RTCSET |
 287                 //BIT_BG_PD_RTCSET |
 288                 0
 289         );
 290
 291         /**********************************************
 292          *   Following is AP LDO A DIE Sleep Control  *
 293          *********************************************/
 294         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL0,
 295                 BIT_SLP_IO_EN |
 296                 BIT_SLP_DCDC_OTP_PD_EN |
 297                 //BIT_SLP_DCDCGEN_PD_EN |
 298                 BIT_SLP_DCDCWPA_PD_EN |
 299                 //BIT_SLP_DCDCWRF_PD_EN |
 300                 BIT_SLP_DCDCARM_PD_EN |
 301                 BIT_SLP_LDOEMMCCORE_PD_EN |
 302                 BIT_SLP_LDOEMMCIO_PD_EN |
 303                 BIT_SLP_LDORF2_PD_EN |
 304                 //BIT_SLP_LDORF1_PD_EN |
 305                 BIT_SLP_LDORF0_PD_EN |
 306                 BIT_SLP_LDOVDD25_PD_EN |
 307                 //BIT_SLP_LDOVDD28_PD_EN |
 308                 //BIT_SLP_LDOVDD18_PD_EN |
 309                 0
 310         );
 311
 312         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL1,
 313                 BIT_SLP_LDO_PD_EN |
 314                 BIT_SLP_LDOLPREF_PD_EN |
 315                 BIT_SLP_LDOCLSG_PD_EN |
 316                 BIT_SLP_LDOUSB_PD_EN |
 317                 BIT_SLP_LDOCAMMOT_PD_EN |
 318                 BIT_SLP_LDOCAMIO_PD_EN |
 319                 BIT_SLP_LDOCAMD_PD_EN |
 320                 BIT_SLP_LDOCAMA_PD_EN |
 321                 BIT_SLP_LDOSIM2_PD_EN |
 322                 //BIT_SLP_LDOSIM1_PD_EN |
 323                 //BIT_SLP_LDOSIM0_PD_EN |
 324                 BIT_SLP_LDOSD_PD_EN |
 325                 BIT_SLP_LDOAVDD18_PD_EN |
 326                 0
 327         );
 328
 329         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL2,
 330                 //BIT_SLP_DCDC_BG_LP_EN |
 331                 //BIT_SLP_DCDCCORE_LP_EN |
 332                 //BIT_SLP_DCDCMEM_LP_EN |
 333                 //BIT_SLP_DCDCARM_LP_EN |
 334                 //BIT_SLP_DCDCGEN_LP_EN |
 335                 //BIT_SLP_DCDCWPA_LP_EN |
 336                 //BIT_SLP_DCDCWRF_LP_EN |
 337                 //BIT_SLP_LDOEMMCCORE_LP_EN |
 338                 //BIT_SLP_LDOEMMCIO_LP_EN |
 339                 //BIT_SLP_LDORF2_LP_EN |
 340                 //BIT_SLP_LDORF1_LP_EN |
 341                 //BIT_SLP_LDORF0_LP_EN |
 342                 0
 343         );
 344
 345         ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL3,
 346                 //BIT_SLP_BG_LP_EN |
 347                 //BIT_SLP_LDOVDD25_LP_EN |
 348                 //BIT_SLP_LDOVDD28_LP_EN |
 349                 //BIT_SLP_LDOVDD18_LP_EN |
 350                 //BIT_SLP_LDOCLSG_LP_EN |
 351                 //BIT_SLP_LDOUSB_LP_EN |
 352                 //BIT_SLP_LDOCAMMOT_LP_EN |
 353                 //BIT_SLP_LDOCAMIO_LP_EN |
 354                 //BIT_SLP_LDOCAMD_LP_EN |
 355                 //BIT_SLP_LDOCAMA_LP_EN |
 356                 //BIT_SLP_LDOSIM2_LP_EN |
 357                 //BIT_SLP_LDOSIM1_LP_EN |
 358                 //BIT_SLP_LDOSIM0_LP_EN |
 359                 //BIT_SLP_LDOSD_LP_EN |
 360                 //BIT_SLP_LDOAVDD18_LP_EN |
 361                 0
 362         );
 363
 364         ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
 365                 BIT_SLP_XTLBUF_PD_EN |
 366                 BIT_XTL_EN |
 367                 BITS_XTL_WAIT(0x32)|
 368                 0
 369         );
 370
 371         ANA_REG_SET(ANA_REG_GLB_DDR2_CTRL,
 372                 BIT_DDR2_BUF_PD_HW |
 373                 BITS_DDR2_BUF_S_DS(0x0) |
 374                 BITS_DDR2_BUF_CHNS_DS(0x0) |
 375                 //BIT_DDR2_BUF_PD |
 376                 BITS_DDR2_BUF_S(0x3) |
 377                 BITS_DDR2_BUF_CHNS(0x0) |
 378                 0
 379         );
 380
 381         /****************************************
 382         *   Following is CP LDO Sleep Control  *
 383         ****************************************/
 384
 385         ANA_REG_SET(ANA_REG_GLB_LDO1828_XTL_CTL,
 386                 //BIT_LDO_VDD18_EXT_XTL2_EN |
 387                 //BIT_LDO_VDD18_EXT_XTL1_EN |
 388                 //BIT_LDO_VDD18_EXT_XTL0_EN |
 389                 //BIT_LDO_VDD18_XTL2_EN     |
 390                 //BIT_LDO_VDD18_XTL1_EN     |
 391                 //BIT_LDO_VDD18_XTL0_EN     |
 392                 //BIT_LDO_VDD28_EXT_XTL2_EN |
 393                 //BIT_LDO_VDD28_EXT_XTL1_EN |
 394                 //BIT_LDO_VDD28_EXT_XTL0_EN |
 395                 //BIT_LDO_VDD28_XTL2_EN     |
 396                 //BIT_LDO_VDD28_XTL1_EN     |
 397                 //BIT_LDO_VDD28_XTL0_EN     |
 398                 0
 399         );
 400
 401         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
 402                 BIT_LDO_XTL_EN |
 403                 //BIT_LDO_RF1_EXT_XTL2_EN |
 404                 //BIT_LDO_RF1_EXT_XTL1_EN |
 405                 //BIT_LDO_RF1_EXT_XTL0_EN |
 406                 //BIT_LDO_RF1_XTL2_EN |
 407                 //BIT_LDO_RF1_XTL1_EN |
 408                 //BIT_LDO_RF1_XTL0_EN |
 409                 //BIT_LDO_RF0_EXT_XTL2_EN |
 410                 //BIT_LDO_RF0_EXT_XTL1_EN |
 411                 //BIT_LDO_RF0_EXT_XTL0_EN |
 412                 BIT_LDO_RF0_XTL2_EN |
 413                 BIT_LDO_RF0_XTL1_EN |
 414                 BIT_LDO_RF0_XTL0_EN |
 415                 0
 416         );
 417
 418         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
 419                 //BIT_LDO_VDD25_EXT_XTL2_EN |
 420                 //BIT_LDO_VDD25_EXT_XTL1_EN |
 421                 //BIT_LDO_VDD25_EXT_XTL0_EN |
 422                 BIT_LDO_VDD25_XTL2_EN |
 423                 BIT_LDO_VDD25_XTL1_EN |
 424                 BIT_LDO_VDD25_XTL0_EN |
 425                 //BIT_LDO_RF2_EXT_XTL2_EN |
 426                 //BIT_LDO_RF2_EXT_XTL1_EN |
 427                 //BIT_LDO_RF2_EXT_XTL0_EN |
 428                 BIT_LDO_RF2_XTL2_EN |
 429                 BIT_LDO_RF2_XTL1_EN |
 430                 BIT_LDO_RF2_XTL0_EN |
 431                 0
 432         );
 433
 434         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
 435                 //BIT_LDO_AVDD18_EXT_XTL2_EN |
 436                 //BIT_LDO_AVDD18_EXT_XTL1_EN |
 437                 //BIT_LDO_AVDD18_EXT_XTL0_EN |
 438                 //BIT_LDO_AVDD18_XTL2_EN |
 439                 //BIT_LDO_AVDD18_XTL1_EN |
 440                 //BIT_LDO_AVDD18_XTL0_EN |
 441                 //BIT_LDO_SIM2_EXT_XTL2_EN |
 442                 //BIT_LDO_SIM2_EXT_XTL1_EN |
 443                 //BIT_LDO_SIM2_EXT_XTL0_EN |
 444                 //BIT_LDO_SIM2_XTL2_EN |
 445                 //BIT_LDO_SIM2_XTL1_EN |
 446                 //BIT_LDO_SIM2_XTL0_EN |
 447                 0
 448         );
 449
 450         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
 451                 //BIT_DCDC_BG_EXT_XTL2_EN |
 452                 //BIT_DCDC_BG_EXT_XTL1_EN |
 453                 //BIT_DCDC_BG_EXT_XTL0_EN |
 454                 BIT_DCDC_BG_XTL2_EN |
 455                 BIT_DCDC_BG_XTL1_EN |
 456                 BIT_DCDC_BG_XTL0_EN |
 457                 //BIT_BG_EXT_XTL2_EN |
 458                 //BIT_BG_EXT_XTL1_EN |
 459                 //BIT_BG_EXT_XTL0_EN |
 460                 //BIT_BG_XTL2_EN |
 461                 //BIT_BG_XTL1_EN |
 462                 //BIT_BG_XTL0_EN |
 463                 0
 464         );
 465
 466         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
 467                 //BIT_DCDC_WRF_XTL2_EN |
 468                 //BIT_DCDC_WRF_XTL1_EN |
 469                 //BIT_DCDC_WRF_XTL0_EN |
 470                 BIT_DCDC_WPA_XTL2_EN |
 471                 //BIT_DCDC_WPA_XTL1_EN |
 472                 //BIT_DCDC_WPA_XTL0_EN |
 473                 BIT_DCDC_MEM_XTL2_EN |
 474                 BIT_DCDC_MEM_XTL1_EN |
 475                 BIT_DCDC_MEM_XTL0_EN |
 476                 BIT_DCDC_GEN_XTL2_EN |
 477                 BIT_DCDC_GEN_XTL1_EN |
 478                 BIT_DCDC_GEN_XTL0_EN |
 479                 BIT_DCDC_CORE_XTL2_EN |
 480                 BIT_DCDC_CORE_XTL1_EN |
 481                 BIT_DCDC_CORE_XTL0_EN |
 482                 0
 483         );
 484
 485         ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN5,
 486                 //BIT_DCDC_WRF_EXT_XTL2_EN |
 487                 //BIT_DCDC_WRF_EXT_XTL1_EN |
 488                 //BIT_DCDC_WRF_EXT_XTL0_EN |
 489                 //BIT_DCDC_WPA_EXT_XTL2_EN |
 490                 //BIT_DCDC_WPA_EXT_XTL1_EN |
 491                 //BIT_DCDC_WPA_EXT_XTL0_EN |
 492                 //BIT_DCDC_MEM_EXT_XTL2_EN |
 493                 //BIT_DCDC_MEM_EXT_XTL1_EN |
 494                 //BIT_DCDC_MEM_EXT_XTL0_EN |
 495                 //BIT_DCDC_GEN_EXT_XTL2_EN |
 496                 //BIT_DCDC_GEN_EXT_XTL1_EN |
 497                 //BIT_DCDC_GEN_EXT_XTL0_EN |
 498                 //BIT_DCDC_CORE_EXT_XTL2_EN |
 499                 //BIT_DCDC_CORE_EXT_XTL1_EN |
 500                 //BIT_DCDC_CORE_EXT_XTL0_EN |
 501                 0
 502         );
 503
 504 #endif
 505         /************************************************
 506         *   Following is AP/CP LDO D DIE Sleep Control   *
 507         *************************************************/
 508
 509         CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
 510                 BIT_XTL0_AP_SEL |
 511                 BIT_XTL0_CP0_SEL |
 512                 BIT_XTL0_CP1_SEL |
 513                 BIT_XTL0_CP2_SEL |
 514                 0
 515         );
 516
 517         CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
 518                 BIT_XTL1_AP_SEL |
 519                 BIT_XTL1_CP0_SEL |
 520                 BIT_XTL1_CP1_SEL |
 521                 BIT_XTL1_CP2_SEL |
 522                 0
 523         );
 524
 525         CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
 526                 //BIT_XTL2_AP_SEL |
 527                 //BIT_XTL2_CP0_SEL |
 528                 //BIT_XTL2_CP1_SEL |
 529                 BIT_XTL2_CP2_SEL |
 530                 0
 531         );
 532
 533         CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
 534                 BIT_XTLBUF0_CP2_SEL |
 535                 BIT_XTLBUF0_CP1_SEL |
 536                 BIT_XTLBUF0_CP0_SEL |
 537                 BIT_XTLBUF0_AP_SEL  |
 538                 0
 539         );
 540
 541         CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
 542                 BIT_XTLBUF1_CP2_SEL |
 543                 BIT_XTLBUF1_CP1_SEL |
 544                 BIT_XTLBUF1_CP0_SEL |
 545                 BIT_XTLBUF1_AP_SEL  |
 546                 0
 547         );
 548
 549         CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
 550                 //BIT_MPLL_REF_SEL |
 551                 //BIT_MPLL_CP2_SEL |
 552                 //BIT_MPLL_CP1_SEL |
 553                 //BIT_MPLL_CP0_SEL |
 554                 BIT_MPLL_AP_SEL  |
 555                 0
 556         );
 557
 558         CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
 559                 //BIT_DPLL_REF_SEL |
 560                 BIT_DPLL_CP2_SEL |
 561                 BIT_DPLL_CP1_SEL |
 562                 BIT_DPLL_CP0_SEL |
 563                 BIT_DPLL_AP_SEL  |
 564                 0
 565         );
 566         /*caution tdpll & wpll sel config in spl*/
 567         reg_val = CHIP_REG_GET(REG_PMU_APB_TDPLL_REL_CFG);
 568         reg_val &= ~0xF;
 569         reg_val |= (
 570                    BIT_TDPLL_CP2_SEL|
 571                    BIT_TDPLL_CP1_SEL|
 572                    BIT_TDPLL_CP0_SEL|
 573                    BIT_TDPLL_AP_SEL |
 574                    0);
 575         CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,reg_val);
 576
 577         reg_val = CHIP_REG_GET(REG_PMU_APB_WPLL_REL_CFG);
 578         reg_val &= ~0xF;
 579         reg_val |= (
 580                    //BIT_WPLL_CP2_SEL|
 581                    //BIT_WPLL_CP1_SEL|
 582                    BIT_WPLL_CP0_SEL|
 583                    //BIT_WPLL_AP_SEL |
 584                    0);
 585         CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,reg_val);
 586
 587         CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
 588                 //BIT_CPLL_REF_SEL |
 589                 BIT_CPLL_CP2_SEL |
 590                 //BIT_CPLL_CP1_SEL |
 591                 //BIT_CPLL_CP0_SEL |
 592                 //BIT_CPLL_AP_SEL  |
 593                 0
 594         );
 595
 596         CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG,
 597                 BIT_WIFIPLL1_REF_SEL |
 598                 BIT_WIFIPLL1_CP2_SEL |
 599                 //BIT_WIFIPLL1_CP1_SEL |
 600                 //BIT_WIFIPLL1_CP0_SEL |
 601                 //BIT_WIFIPLL1_AP_SEL |
 602                 0
 603         );
 604
 605         CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG,
 606                 BIT_WIFIPLL2_REF_SEL |
 607                 BIT_WIFIPLL2_CP2_SEL |
 608                 //BIT_WIFIPLL2_CP1_SEL |
 609                 //BIT_WIFIPLL2_CP0_SEL |
 610                 //BIT_WIFIPLL2_AP_SEL |
 611                 0
 612         );
 613
 614         CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
 615                 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN         |
 616                 BITS_PD_CA7_TOP_PWR_ON_DLY(8)           |
 617                 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2)       |
 618                 BITS_PD_CA7_TOP_ISO_ON_DLY(4)           |
 619                 0
 620         );
 621
 622         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
 623                 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN          |
 624                 BITS_PD_CA7_C0_PWR_ON_DLY(8)            |
 625                 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6)        |
 626                 BITS_PD_CA7_C0_ISO_ON_DLY(2)            |
 627                 0
 628         );
 629
 630         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
 631                 BIT_PD_CA7_C1_FORCE_SHUTDOWN            |
 632                 BITS_PD_CA7_C1_PWR_ON_DLY(8)            |
 633                 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4)        |
 634                 BITS_PD_CA7_C1_ISO_ON_DLY(2)            |
 635                 0
 636         );
 637
 638         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
 639                 BIT_PD_CA7_C2_FORCE_SHUTDOWN            |
 640                 BITS_PD_CA7_C2_PWR_ON_DLY(8)            |
 641                 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4)        |
 642                 BITS_PD_CA7_C2_ISO_ON_DLY(2)            |
 643                 0
 644         );
 645
 646         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
 647                 BIT_PD_CA7_C3_FORCE_SHUTDOWN            |
 648                 BITS_PD_CA7_C3_PWR_ON_DLY(8)            |
 649                 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4)        |
 650                 BITS_PD_CA7_C3_ISO_ON_DLY(2)            |
 651                 0
 652         );
 653
 654         CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
 655                 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN          |
 656                 BITS_PD_AP_SYS_PWR_ON_DLY(8)            |
 657                 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0)        |
 658                 BITS_PD_AP_SYS_ISO_ON_DLY(6)            |
 659                 0
 660         );
 661
 662         CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
 663                 BIT_PD_MM_TOP_FORCE_SHUTDOWN            |
 664                 BITS_PD_MM_TOP_PWR_ON_DLY(8)            |
 665                 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0)        |
 666                 BITS_PD_MM_TOP_ISO_ON_DLY(4)            |
 667                 0
 668         );
 669
 670         CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
 671                 BIT_PD_GPU_TOP_FORCE_SHUTDOWN           |
 672                 BITS_PD_GPU_TOP_PWR_ON_DLY(8)   |
 673                 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0)       |
 674                 BITS_PD_GPU_TOP_ISO_ON_DLY(4)           |
 675                 0
 676         );
 677
 678         CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
 679                 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN         |
 680                 BITS_PD_PUB_SYS_PWR_ON_DLY(8)           |
 681                 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0)       |
 682                 BITS_PD_PUB_SYS_ISO_ON_DLY(6)           |
 683                 0
 684         );
 685
 686         CHIP_REG_SET(REG_PMU_APB_PD_DDR_PUBL_CFG,
 687                 BIT_PD_DDR_PUBL_AUTO_SHUTDOWN_EN        |
 688                 BITS_PD_DDR_PUBL_PWR_ON_DLY(8)          |
 689                 BITS_PD_DDR_PUBL_PWR_ON_SEQ_DLY(0)      |
 690                 BITS_PD_DDR_PUBL_ISO_ON_DLY(6)          |
 691                 0
 692         );
 693
 694         CHIP_REG_SET(REG_PMU_APB_PD_DDR_PHY_CFG,
 695                 BIT_PD_DDR_PHY_AUTO_SHUTDOWN_EN         |
 696                 BITS_PD_DDR_PHY_PWR_ON_DLY(8)           |
 697                 BITS_PD_DDR_PHY_PWR_ON_SEQ_DLY(0)       |
 698                 BITS_PD_DDR_PHY_ISO_ON_DLY(6)           |
 699                 0
 700         );
 701
 702         CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
 703                 BITS_XTL1_WAIT_CNT(0x39)                |
 704                 BITS_XTL0_WAIT_CNT(0x39)                |
 705                 0
 706         );
 707
 708         CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
 709                 BITS_XTLBUF1_WAIT_CNT(7)                |
 710                 BITS_XTLBUF0_WAIT_CNT(7)                |
 711                 0
 712         );
 713
 714         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
 715                 BITS_WPLL_WAIT_CNT(7)                   |
 716                 BITS_TDPLL_WAIT_CNT(7)                  |
 717                 BITS_DPLL_WAIT_CNT(7)                   |
 718                 BITS_MPLL_WAIT_CNT(7)                   |
 719                 0
 720         );
 721
 722         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
 723                 BITS_WIFIPLL2_WAIT_CNT(7)               |
 724                 BITS_WIFIPLL1_WAIT_CNT(7)               |
 725                 BITS_CPLL_WAIT_CNT(7)                   |
 726                 0
 727         );
 728
 729         ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
 730                 BITS_SLP_IN_WAIT_DCDCARM(7)             |
 731                 BITS_SLP_OUT_WAIT_DCDCARM(8)            |
 732                 0
 733         );
 734         /*chip service package init*/
 735         CSP_Init(0);
 736 }