3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 * Copyright (C) 2012 Stefan Roese <sr@denx.de>
7 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/spr_defs.h>
18 #include <asm/arch/spr_misc.h>
19 #include <linux/mtd/fsmc_nand.h>
22 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
27 * X600 is equipped with an M41T82 RTC. This RTC has the
28 * HT bit (Halt Update), which needs to be cleared upon
29 * power-up. Otherwise the RTC is halted.
33 return spear_board_init(MACH_TYPE_SPEAR600);
36 int board_late_init(void)
39 * Monitor and env protection on by default
41 flash_protect(FLAG_PROTECT_SET,
42 CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
43 CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
44 2 * CONFIG_ENV_SECT_SIZE - 1,
47 /* Init FPGA subsystem */
54 * board_nand_init - Board specific NAND initialization
55 * @nand: mtd private chip structure
57 * Called by nand_init_chip to initialize the board specific functions
60 void board_nand_init(void)
62 struct misc_regs *const misc_regs_p =
63 (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
64 struct nand_chip *nand = &nand_chip[0];
66 if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
70 int designware_board_phy_init(struct eth_device *dev, int phy_addr,
71 int (*mii_write)(struct eth_device *, u8, u8, u16),
72 int dw_reset_phy(struct eth_device *))
74 /* Extended PHY control 1, select GMII */
75 mii_write(dev, phy_addr, 23, 0x0020);
77 /* Software reset necessary after GMII mode selction */
80 /* Enable extended page register access */
81 mii_write(dev, phy_addr, 31, 0x0001);
83 /* 17e: Enhanced LED behavior, needs to be written twice */
84 mii_write(dev, phy_addr, 17, 0x09ff);
85 mii_write(dev, phy_addr, 17, 0x09ff);
87 /* 16e: Enhanced LED method select */
88 mii_write(dev, phy_addr, 16, 0xe0ea);
90 /* Disable extended page register access */
91 mii_write(dev, phy_addr, 31, 0x0000);
93 /* Enable clock output pin */
94 mii_write(dev, phy_addr, 18, 0x0049);
99 int board_eth_init(bd_t *bis)
103 if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR,
104 PHY_INTERFACE_MODE_GMII) >= 0)