board/somlabs/visionsom-6ull/visionsom-6ull.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017-2019 A. Karas, SomLabs
   4  * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <init.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/crm_regs.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/gpio.h>
  15 #include <asm/mach-imx/boot_mode.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/mach-imx/mxc_i2c.h>
  18 #include <asm/io.h>
  19 #include <common.h>
  20 #include <env.h>
  21 #include <fsl_esdhc_imx.h>
  22 #include <i2c.h>
  23 #include <miiphy.h>
  24 #include <linux/sizes.h>
  25 #include <mmc.h>
  26 #include <netdev.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  31         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  32         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  33
  34 int dram_init(void)
  35 {
  36         gd->ram_size = imx_ddr_size();
  37
  38         return 0;
  39 }
  40
  41 static iomux_v3_cfg_t const uart1_pads[] = {
  42         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  43         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  44 };
  45
  46 static void setup_iomux_uart(void)
  47 {
  48         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  49 }
  50
  51 #ifdef CONFIG_FEC_MXC
  52 static int setup_fec(void)
  53 {
  54         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  55         int ret;
  56
  57         /*
  58          * Use 50M anatop loopback REF_CLK1 for ENET1,
  59          * clear gpr1[13], set gpr1[17].
  60          */
  61         clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  62                         IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  63
  64         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
  65         if (ret)
  66                 return ret;
  67
  68         enable_enet_clk(1);
  69
  70         return 0;
  71 }
  72
  73 int board_phy_config(struct phy_device *phydev)
  74 {
  75         phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  76
  77         if (phydev->drv->config)
  78                 phydev->drv->config(phydev);
  79
  80         return 0;
  81 }
  82 #endif
  83
  84 int board_mmc_get_env_dev(int devno)
  85 {
  86         return devno;
  87 }
  88
  89 int mmc_map_to_kernel_blk(int devno)
  90 {
  91         return devno;
  92 }
  93
  94 int board_early_init_f(void)
  95 {
  96         setup_iomux_uart();
  97
  98         return 0;
  99 }
 100
 101 int board_init(void)
 102 {
 103         /* Address of boot parameters */
 104         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 105
 106 #ifdef CONFIG_SYS_I2C
 107         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 108 #endif
 109
 110 #ifdef CONFIG_FEC_MXC
 111         setup_fec();
 112 #endif
 113
 114         return 0;
 115 }
 116
 117 #ifdef CONFIG_CMD_BMODE
 118 static const struct boot_mode board_boot_modes[] = {
 119         /* 4 bit bus width */
 120         {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
 121         {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 122         {NULL,   0},
 123 };
 124 #endif
 125
 126 int board_late_init(void)
 127 {
 128 #ifdef CONFIG_CMD_BMODE
 129         add_board_boot_modes(board_boot_modes);
 130 #endif
 131
 132         if (is_cpu_type(MXC_CPU_MX6ULL))
 133                 env_set("board", "visionsom-6ull");
 134         else
 135                 env_set("board", "visionsom-6ul");
 136
 137         return 0;
 138 }
 139
 140 int checkboard(void)
 141 {
 142         printf("Board: SoMLabs VisionSOM-6UL%s\n",
 143                is_cpu_type(MXC_CPU_MX6ULL) ? "L" : "");
 144
 145         return 0;
 146 }