board/solidrun/mx6cuboxi/mx6cuboxi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2022 Josua Mayer <josua@solid-run.com>
   4  *
   5  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   6  *
   7  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   8  *
   9  * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
  10  *
  11  * Based on SPL code from Solidrun tree, which is:
  12  * Author: Tungyi Lin <tungyilin1127@gmail.com>
  13  *
  14  * Derived from EDM_CF_IMX6 code by TechNexion,Inc
  15  * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
  16  */
  17
  18 #include <common.h>
  19 #include <image.h>
  20 #include <init.h>
  21 #include <log.h>
  22 #include <asm/arch/clock.h>
  23 #include <asm/arch/imx-regs.h>
  24 #include <asm/arch/iomux.h>
  25 #include <asm/arch/mx6-pins.h>
  26 #include <asm/arch/mxc_hdmi.h>
  27 #include <env.h>
  28 #include <asm/global_data.h>
  29 #include <linux/delay.h>
  30 #include <linux/errno.h>
  31 #include <asm/gpio.h>
  32 #include <asm/mach-imx/iomux-v3.h>
  33 #include <asm/mach-imx/sata.h>
  34 #include <asm/mach-imx/video.h>
  35 #include <mmc.h>
  36 #include <fsl_esdhc_imx.h>
  37 #include <malloc.h>
  38 #include <asm/arch/crm_regs.h>
  39 #include <asm/io.h>
  40 #include <asm/arch/sys_proto.h>
  41 #include <spl.h>
  42 #include <usb.h>
  43 #include <usb/ehci-ci.h>
  44 #include <netdev.h>
  45 #include <phy.h>
  46
  47 DECLARE_GLOBAL_DATA_PTR;
  48
  49 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  50         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  51         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  52
  53 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  54         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  55         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  56
  57 #define USB_H1_VBUS     IMX_GPIO_NR(1, 0)
  58
  59 enum board_type {
  60         CUBOXI          = 0x00,
  61         HUMMINGBOARD    = 0x01,
  62         HUMMINGBOARD2   = 0x02,
  63         UNKNOWN         = 0x03,
  64 };
  65
  66 static struct gpio_desc board_detect_desc[5];
  67
  68 #define MEM_STRIDE 0x4000000
  69 static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
  70 {
  71         volatile u32 *addr;
  72         u32          save[64];
  73         u32          cnt;
  74         u32          size;
  75         int          i = 0;
  76
  77         /* First save the data */
  78         for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) {
  79                 addr = (volatile u32 *)((u32)base + cnt);       /* pointer arith! */
  80                 sync ();
  81                 save[i++] = *addr;
  82                 sync ();
  83         }
  84
  85         /* First write a signature */
  86         * (volatile u32 *)base = 0x12345678;
  87         for (size = MEM_STRIDE; size < maxsize; size += MEM_STRIDE) {
  88                 * (volatile u32 *)((u32)base + size) = size;
  89                 sync ();
  90                 if (* (volatile u32 *)((u32)base) == size) {    /* We reached the overlapping address */
  91                         break;
  92                 }
  93         }
  94
  95         /* Restore the data */
  96         for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) {
  97                 addr = (volatile u32 *)((u32)base + cnt);       /* pointer arith! */
  98                 sync ();
  99                 *addr = save[i--];
 100                 sync ();
 101         }
 102
 103         return (size);
 104 }
 105
 106 int dram_init(void)
 107 {
 108         u32 max_size = imx_ddr_size();
 109
 110         gd->ram_size = get_ram_size_stride_test((u32 *) CFG_SYS_SDRAM_BASE,
 111                                                 (u32)max_size);
 112
 113         return 0;
 114 }
 115
 116 static iomux_v3_cfg_t const uart1_pads[] = {
 117         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 118         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 119 };
 120
 121 static iomux_v3_cfg_t const usdhc2_pads[] = {
 122         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 123         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 124         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 125         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 126         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 127         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 128 };
 129
 130 static iomux_v3_cfg_t const usdhc3_pads[] = {
 131         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 132         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 133         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 134         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 135         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 136         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 137         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 138         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 139         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 140         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 141         IOMUX_PADS(PAD_SD3_RST__SD3_RESET       | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 142 };
 143
 144 static iomux_v3_cfg_t const board_detect[] = {
 145         /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
 146         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 147         IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04   | MUX_PAD_CTRL(UART_PAD_CTRL)),
 148         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 149 };
 150
 151 static iomux_v3_cfg_t const som_rev_detect[] = {
 152         /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
 153         IOMUX_PADS(PAD_CSI0_DAT14__GPIO6_IO00  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 154         IOMUX_PADS(PAD_CSI0_DAT18__GPIO6_IO04  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 155 };
 156
 157 static void setup_iomux_uart(void)
 158 {
 159         SETUP_IOMUX_PADS(uart1_pads);
 160 }
 161
 162 int board_mmc_get_env_dev(int devno)
 163 {
 164         return devno;
 165 }
 166
 167 #ifdef CONFIG_VIDEO_IPUV3
 168 static void do_enable_hdmi(struct display_info_t const *dev)
 169 {
 170         imx_enable_hdmi_phy();
 171 }
 172
 173 struct display_info_t const displays[] = {
 174         {
 175                 .bus    = -1,
 176                 .addr   = 0,
 177                 .pixfmt = IPU_PIX_FMT_RGB24,
 178                 .detect = detect_hdmi,
 179                 .enable = do_enable_hdmi,
 180                 .mode   = {
 181                         .name           = "HDMI",
 182                         /* 1024x768@60Hz (VESA)*/
 183                         .refresh        = 60,
 184                         .xres           = 1024,
 185                         .yres           = 768,
 186                         .pixclock       = 15384,
 187                         .left_margin    = 160,
 188                         .right_margin   = 24,
 189                         .upper_margin   = 29,
 190                         .lower_margin   = 3,
 191                         .hsync_len      = 136,
 192                         .vsync_len      = 6,
 193                         .sync           = FB_SYNC_EXT,
 194                         .vmode          = FB_VMODE_NONINTERLACED
 195                 }
 196         }
 197 };
 198
 199 size_t display_count = ARRAY_SIZE(displays);
 200
 201 static int setup_display(void)
 202 {
 203         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 204         int reg;
 205         int timeout = 100000;
 206
 207         enable_ipu_clock();
 208         imx_setup_hdmi();
 209
 210         /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
 211         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 212
 213         reg = readl(&ccm->analog_pll_video);
 214         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 215         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
 216         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 217         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
 218         writel(reg, &ccm->analog_pll_video);
 219
 220         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 221         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 222
 223         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 224         writel(reg, &ccm->analog_pll_video);
 225
 226         while (timeout--)
 227                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 228                         break;
 229         if (timeout < 0) {
 230                 printf("Warning: video pll lock timeout!\n");
 231                 return -ETIMEDOUT;
 232         }
 233
 234         reg = readl(&ccm->analog_pll_video);
 235         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 236         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 237         writel(reg, &ccm->analog_pll_video);
 238
 239         /* gate ipu1_di0_clk */
 240         clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 241
 242         /* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
 243         reg = readl(&ccm->chsccdr);
 244         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
 245                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
 246                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 247         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
 248                (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
 249                (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 250         writel(reg, &ccm->chsccdr);
 251
 252         /* enable ipu1_di0_clk */
 253         setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 254
 255         return 0;
 256 }
 257 #endif /* CONFIG_VIDEO_IPUV3 */
 258
 259 static int setup_fec(void)
 260 {
 261         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 262         int ret;
 263
 264         ret = enable_fec_anatop_clock(0, ENET_25MHZ);
 265         if (ret)
 266                 return ret;
 267
 268         /* set gpr1[ENET_CLK_SEL] */
 269         setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 270
 271         return 0;
 272 }
 273
 274 int board_early_init_f(void)
 275 {
 276         setup_iomux_uart();
 277
 278         if (CONFIG_IS_ENABLED(SATA))
 279                 setup_sata();
 280         setup_fec();
 281
 282         return 0;
 283 }
 284
 285 int board_init(void)
 286 {
 287         int ret = 0;
 288
 289         /* address of boot parameters */
 290         gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
 291
 292 #ifdef CONFIG_VIDEO_IPUV3
 293         ret = setup_display();
 294 #endif
 295
 296         return ret;
 297 }
 298
 299 static int request_detect_gpios(void)
 300 {
 301         int node;
 302         int ret;
 303
 304         node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
 305                 "solidrun,hummingboard-detect");
 306         if (node < 0)
 307                 return -ENODEV;
 308
 309         ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
 310                 "detect-gpios", board_detect_desc,
 311                 ARRAY_SIZE(board_detect_desc), GPIOD_IS_IN);
 312
 313         return ret;
 314 }
 315
 316 static int free_detect_gpios(void)
 317 {
 318         return gpio_free_list_nodev(board_detect_desc,
 319                 ARRAY_SIZE(board_detect_desc));
 320 }
 321
 322 static enum board_type board_type(void)
 323 {
 324         int val1, val2, val3;
 325
 326         SETUP_IOMUX_PADS(board_detect);
 327
 328         /*
 329          * Machine selection -
 330          * Machine      val1, val2, val3
 331          * ----------------------------
 332          * HB2            x     x    0
 333          * HB rev 3.x     x     0    x
 334          * CBi            0     1    x
 335          * HB             1     1    x
 336          */
 337
 338         gpio_direction_input(IMX_GPIO_NR(2, 8));
 339         val3 = gpio_get_value(IMX_GPIO_NR(2, 8));
 340
 341         if (val3 == 0)
 342                 return HUMMINGBOARD2;
 343
 344         gpio_direction_input(IMX_GPIO_NR(3, 4));
 345         val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
 346
 347         if (val2 == 0)
 348                 return HUMMINGBOARD;
 349
 350         gpio_direction_input(IMX_GPIO_NR(4, 9));
 351         val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
 352
 353         if (val1 == 0) {
 354                 return CUBOXI;
 355         } else {
 356                 return HUMMINGBOARD;
 357         }
 358 }
 359
 360 static bool is_rev_15_som(void)
 361 {
 362         int val1, val2;
 363         SETUP_IOMUX_PADS(som_rev_detect);
 364
 365         val1 = gpio_get_value(IMX_GPIO_NR(6, 0));
 366         val2 = gpio_get_value(IMX_GPIO_NR(6, 4));
 367
 368         if (val1 == 1 && val2 == 0)
 369                 return true;
 370
 371         return false;
 372 }
 373
 374 static bool has_emmc(void)
 375 {
 376         struct mmc *mmc;
 377         mmc = find_mmc_device(2);
 378         if (!mmc)
 379                 return 0;
 380         return (mmc_get_op_cond(mmc, true) < 0) ? 0 : 1;
 381 }
 382
 383 int checkboard(void)
 384 {
 385         request_detect_gpios();
 386
 387         switch (board_type()) {
 388         case CUBOXI:
 389                 puts("Board: MX6 Cubox-i");
 390                 break;
 391         case HUMMINGBOARD:
 392                 puts("Board: MX6 HummingBoard");
 393                 break;
 394         case HUMMINGBOARD2:
 395                 puts("Board: MX6 HummingBoard2");
 396                 break;
 397         case UNKNOWN:
 398         default:
 399                 puts("Board: Unknown\n");
 400                 goto out;
 401         }
 402
 403         if (is_rev_15_som())
 404                 puts(" (som rev 1.5)\n");
 405         else
 406                 puts("\n");
 407
 408         free_detect_gpios();
 409 out:
 410         return 0;
 411 }
 412
 413 static int find_ethernet_phy(void)
 414 {
 415         struct mii_dev *bus = NULL;
 416         struct phy_device *phydev = NULL;
 417         int phy_addr = -ENOENT;
 418
 419 #ifdef CONFIG_FEC_MXC
 420         bus = fec_get_miibus(ENET_BASE_ADDR, -1);
 421         if (!bus)
 422                 return -ENOENT;
 423
 424         // scan address 0, 1, 4
 425         phydev = phy_find_by_mask(bus, 0b00010011);
 426         if (!phydev) {
 427                 free(bus);
 428                 return -ENOENT;
 429         }
 430         pr_debug("%s: detected ethernet phy at address %d\n", __func__, phydev->addr);
 431         phy_addr = phydev->addr;
 432
 433         free(phydev);
 434 #endif
 435
 436         return phy_addr;
 437 }
 438
 439 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 440 /*
 441  * Configure the correct ethernet PHYs nodes in device-tree:
 442  * - AR8035 at addresses 0 or 4: Cubox
 443  * - AR8035 at address 0: HummingBoard, HummingBoard 2
 444  * - ADIN1300 at address 1: since SoM rev 1.9
 445  */
 446 int ft_board_setup(void *fdt, struct bd_info *bd)
 447 {
 448         int node_phy0, node_phy1, node_phy4;
 449         int ret, phy;
 450         bool enable_phy0 = false, enable_phy1 = false, enable_phy4 = false;
 451         enum board_type board;
 452
 453         // detect device
 454         request_detect_gpios();
 455         board = board_type();
 456         free_detect_gpios();
 457
 458         // detect phy
 459         phy = find_ethernet_phy();
 460         if (phy == 0 || phy == 4) {
 461                 enable_phy0 = true;
 462                 switch (board) {
 463                 case HUMMINGBOARD:
 464                 case HUMMINGBOARD2:
 465                         /* atheros phy may appear only at address 0 */
 466                         break;
 467                 case CUBOXI:
 468                 case UNKNOWN:
 469                 default:
 470                         /* atheros phy may appear at either address 0 or 4 */
 471                         enable_phy4 = true;
 472                 }
 473         } else if (phy == 1) {
 474                 enable_phy1 = true;
 475         } else {
 476                 pr_err("%s: couldn't detect ethernet phy, not patching dtb!\n", __func__);
 477                 return 0;
 478         }
 479
 480         // update all phy nodes status
 481         node_phy0 = fdt_path_offset(fdt, "/soc/bus@2100000/ethernet@2188000/mdio/ethernet-phy@0");
 482         ret = fdt_setprop_string(fdt, node_phy0, "status", enable_phy0 ? "okay" : "disabled");
 483         if (ret < 0 && enable_phy0)
 484                 pr_err("%s: failed to enable ethernet phy at address 0 in dtb!\n", __func__);
 485         node_phy1 = fdt_path_offset(fdt, "/soc/bus@2100000/ethernet@2188000/mdio/ethernet-phy@1");
 486         ret = fdt_setprop_string(fdt, node_phy1, "status", enable_phy1 ? "okay" : "disabled");
 487         if (ret < 0 && enable_phy1)
 488                 pr_err("%s: failed to enable ethernet phy at address 1 in dtb!\n", __func__);
 489         node_phy4 = fdt_path_offset(fdt, "/soc/bus@2100000/ethernet@2188000/mdio/ethernet-phy@4");
 490         ret = fdt_setprop_string(fdt, node_phy4, "status", enable_phy4 ? "okay" : "disabled");
 491         if (ret < 0 && enable_phy4)
 492                 pr_err("%s: failed to enable ethernet phy at address 4 in dtb!\n", __func__);
 493
 494         return 0;
 495 }
 496 #endif
 497
 498 /* Override the default implementation, DT model is not accurate */
 499 int show_board_info(void)
 500 {
 501         return checkboard();
 502 }
 503
 504 int board_late_init(void)
 505 {
 506 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 507         request_detect_gpios();
 508
 509         switch (board_type()) {
 510         case CUBOXI:
 511                 env_set("board_name", "CUBOXI");
 512                 break;
 513         case HUMMINGBOARD:
 514                 env_set("board_name", "HUMMINGBOARD");
 515                 break;
 516         case HUMMINGBOARD2:
 517                 env_set("board_name", "HUMMINGBOARD2");
 518                 break;
 519         case UNKNOWN:
 520         default:
 521                 env_set("board_name", "CUBOXI");
 522         }
 523
 524         if (is_mx6dq())
 525                 env_set("board_rev", "MX6Q");
 526         else
 527                 env_set("board_rev", "MX6DL");
 528
 529         if (is_rev_15_som())
 530                 env_set("som_rev", "V15");
 531
 532         if (has_emmc())
 533                 env_set("has_emmc", "yes");
 534
 535         free_detect_gpios();
 536 #endif
 537
 538         return 0;
 539 }
 540
 541 /*
 542  * This is not a perfect match. Avoid dependency on the DM GPIO driver needed
 543  * for accurate board detection. Hummingboard2 DT is good enough for U-Boot on
 544  * all Hummingboard/Cubox-i platforms.
 545  */
 546 int board_fit_config_name_match(const char *name)
 547 {
 548         char tmp_name[36];
 549
 550         snprintf(tmp_name, sizeof(tmp_name), "%s-hummingboard2-emmc-som-v15",
 551                         is_mx6dq() ? "imx6q" : "imx6dl");
 552
 553         return strcmp(name, tmp_name);
 554 }
 555
 556 void board_boot_order(u32 *spl_boot_list)
 557 {
 558         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 559         unsigned int reg = readl(&psrc->sbmr1) >> 11;
 560         u32 boot_mode = imx6_src_get_boot_mode() & IMX6_BMODE_MASK;
 561         unsigned int bmode = readl(&src_base->sbmr2);
 562
 563         /* If bmode is serial or USB phy is active, return serial */
 564         if (((bmode >> 24) & 0x03) == 0x01 || is_usbotg_phy_active()) {
 565                 spl_boot_list[0] = BOOT_DEVICE_BOARD;
 566                 return;
 567         }
 568
 569         switch (boot_mode >> IMX6_BMODE_SHIFT) {
 570         case IMX6_BMODE_SD:
 571         case IMX6_BMODE_ESD:
 572         case IMX6_BMODE_MMC:
 573         case IMX6_BMODE_EMMC:
 574                 /*
 575                  * Upon reading BOOT_CFG register the following map is done:
 576                  * Bit 11 and 12 of BOOT_CFG register can determine the current
 577                  * mmc port
 578                  * 0x1                  SD2
 579                  * 0x2                  SD3
 580                  */
 581
 582                 reg &= 0x3; /* Only care about bottom 2 bits */
 583                 switch (reg) {
 584                 case 1:
 585                         SETUP_IOMUX_PADS(usdhc2_pads);
 586                         spl_boot_list[0] = BOOT_DEVICE_MMC1;
 587                         break;
 588                 case 2:
 589                         SETUP_IOMUX_PADS(usdhc3_pads);
 590                         spl_boot_list[0] = BOOT_DEVICE_MMC2;
 591                         break;
 592                 }
 593                 break;
 594         default:
 595                 /* By default use USB downloader */
 596                 spl_boot_list[0] = BOOT_DEVICE_BOARD;
 597                 break;
 598         }
 599
 600         /* As a last resort, use serial downloader */
 601         spl_boot_list[1] = BOOT_DEVICE_BOARD;
 602 }
 603
 604 #ifdef CONFIG_SPL_BUILD
 605 #include <asm/arch/mx6-ddr.h>
 606 static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
 607         .dram_sdclk_0 =  0x00020030,
 608         .dram_sdclk_1 =  0x00020030,
 609         .dram_cas =  0x00020030,
 610         .dram_ras =  0x00020030,
 611         .dram_reset =  0x000c0030,
 612         .dram_sdcke0 =  0x00003000,
 613         .dram_sdcke1 =  0x00003000,
 614         .dram_sdba2 =  0x00000000,
 615         .dram_sdodt0 =  0x00003030,
 616         .dram_sdodt1 =  0x00003030,
 617         .dram_sdqs0 =  0x00000030,
 618         .dram_sdqs1 =  0x00000030,
 619         .dram_sdqs2 =  0x00000030,
 620         .dram_sdqs3 =  0x00000030,
 621         .dram_sdqs4 =  0x00000030,
 622         .dram_sdqs5 =  0x00000030,
 623         .dram_sdqs6 =  0x00000030,
 624         .dram_sdqs7 =  0x00000030,
 625         .dram_dqm0 =  0x00020030,
 626         .dram_dqm1 =  0x00020030,
 627         .dram_dqm2 =  0x00020030,
 628         .dram_dqm3 =  0x00020030,
 629         .dram_dqm4 =  0x00020030,
 630         .dram_dqm5 =  0x00020030,
 631         .dram_dqm6 =  0x00020030,
 632         .dram_dqm7 =  0x00020030,
 633 };
 634
 635 static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
 636         .dram_sdclk_0 = 0x00000028,
 637         .dram_sdclk_1 = 0x00000028,
 638         .dram_cas =     0x00000028,
 639         .dram_ras =     0x00000028,
 640         .dram_reset =   0x000c0028,
 641         .dram_sdcke0 =  0x00003000,
 642         .dram_sdcke1 =  0x00003000,
 643         .dram_sdba2 =   0x00000000,
 644         .dram_sdodt0 =  0x00003030,
 645         .dram_sdodt1 =  0x00003030,
 646         .dram_sdqs0 =   0x00000028,
 647         .dram_sdqs1 =   0x00000028,
 648         .dram_sdqs2 =   0x00000028,
 649         .dram_sdqs3 =   0x00000028,
 650         .dram_sdqs4 =   0x00000028,
 651         .dram_sdqs5 =   0x00000028,
 652         .dram_sdqs6 =   0x00000028,
 653         .dram_sdqs7 =   0x00000028,
 654         .dram_dqm0 =    0x00000028,
 655         .dram_dqm1 =    0x00000028,
 656         .dram_dqm2 =    0x00000028,
 657         .dram_dqm3 =    0x00000028,
 658         .dram_dqm4 =    0x00000028,
 659         .dram_dqm5 =    0x00000028,
 660         .dram_dqm6 =    0x00000028,
 661         .dram_dqm7 =    0x00000028,
 662 };
 663
 664 static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
 665         .grp_ddr_type =  0x000C0000,
 666         .grp_ddrmode_ctl =  0x00020000,
 667         .grp_ddrpke =  0x00000000,
 668         .grp_addds =  0x00000030,
 669         .grp_ctlds =  0x00000030,
 670         .grp_ddrmode =  0x00020000,
 671         .grp_b0ds =  0x00000030,
 672         .grp_b1ds =  0x00000030,
 673         .grp_b2ds =  0x00000030,
 674         .grp_b3ds =  0x00000030,
 675         .grp_b4ds =  0x00000030,
 676         .grp_b5ds =  0x00000030,
 677         .grp_b6ds =  0x00000030,
 678         .grp_b7ds =  0x00000030,
 679 };
 680
 681 static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 682         .grp_ddr_type = 0x000c0000,
 683         .grp_ddrmode_ctl = 0x00020000,
 684         .grp_ddrpke = 0x00000000,
 685         .grp_addds = 0x00000028,
 686         .grp_ctlds = 0x00000028,
 687         .grp_ddrmode = 0x00020000,
 688         .grp_b0ds = 0x00000028,
 689         .grp_b1ds = 0x00000028,
 690         .grp_b2ds = 0x00000028,
 691         .grp_b3ds = 0x00000028,
 692         .grp_b4ds = 0x00000028,
 693         .grp_b5ds = 0x00000028,
 694         .grp_b6ds = 0x00000028,
 695         .grp_b7ds = 0x00000028,
 696 };
 697
 698 /* microSOM with Dual processor and 1GB memory */
 699 static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
 700         .p0_mpwldectrl0 =  0x00000000,
 701         .p0_mpwldectrl1 =  0x00000000,
 702         .p1_mpwldectrl0 =  0x00000000,
 703         .p1_mpwldectrl1 =  0x00000000,
 704         .p0_mpdgctrl0 =    0x0314031c,
 705         .p0_mpdgctrl1 =    0x023e0304,
 706         .p1_mpdgctrl0 =    0x03240330,
 707         .p1_mpdgctrl1 =    0x03180260,
 708         .p0_mprddlctl =    0x3630323c,
 709         .p1_mprddlctl =    0x3436283a,
 710         .p0_mpwrdlctl =    0x36344038,
 711         .p1_mpwrdlctl =    0x422a423c,
 712 };
 713
 714 /* microSOM with Quad processor and 2GB memory */
 715 static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
 716         .p0_mpwldectrl0 =  0x00000000,
 717         .p0_mpwldectrl1 =  0x00000000,
 718         .p1_mpwldectrl0 =  0x00000000,
 719         .p1_mpwldectrl1 =  0x00000000,
 720         .p0_mpdgctrl0 =    0x0314031c,
 721         .p0_mpdgctrl1 =    0x023e0304,
 722         .p1_mpdgctrl0 =    0x03240330,
 723         .p1_mpdgctrl1 =    0x03180260,
 724         .p0_mprddlctl =    0x3630323c,
 725         .p1_mprddlctl =    0x3436283a,
 726         .p0_mpwrdlctl =    0x36344038,
 727         .p1_mpwrdlctl =    0x422a423c,
 728 };
 729
 730 /* microSOM with Solo processor and 512MB memory */
 731 static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
 732         .p0_mpwldectrl0 = 0x0045004D,
 733         .p0_mpwldectrl1 = 0x003A0047,
 734         .p0_mpdgctrl0 =   0x023C0224,
 735         .p0_mpdgctrl1 =   0x02000220,
 736         .p0_mprddlctl =   0x44444846,
 737         .p0_mpwrdlctl =   0x32343032,
 738 };
 739
 740 /* microSOM with Dual lite processor and 1GB memory */
 741 static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
 742         .p0_mpwldectrl0 =  0x0045004D,
 743         .p0_mpwldectrl1 =  0x003A0047,
 744         .p1_mpwldectrl0 =  0x001F001F,
 745         .p1_mpwldectrl1 =  0x00210035,
 746         .p0_mpdgctrl0 =    0x023C0224,
 747         .p0_mpdgctrl1 =    0x02000220,
 748         .p1_mpdgctrl0 =    0x02200220,
 749         .p1_mpdgctrl1 =    0x02040208,
 750         .p0_mprddlctl =    0x44444846,
 751         .p1_mprddlctl =    0x4042463C,
 752         .p0_mpwrdlctl =    0x32343032,
 753         .p1_mpwrdlctl =    0x36363430,
 754 };
 755
 756 static struct mx6_ddr3_cfg mem_ddr_2g = {
 757         .mem_speed = 1600,
 758         .density   = 2,
 759         .width     = 16,
 760         .banks     = 8,
 761         .rowaddr   = 14,
 762         .coladdr   = 10,
 763         .pagesz    = 2,
 764         .trcd      = 1375,
 765         .trcmin    = 4875,
 766         .trasmin   = 3500,
 767 };
 768
 769 static struct mx6_ddr3_cfg mem_ddr_4g = {
 770         .mem_speed = 1600,
 771         .density = 4,
 772         .width = 16,
 773         .banks = 8,
 774         .rowaddr = 16,
 775         .coladdr = 10,
 776         .pagesz = 2,
 777         .trcd = 1375,
 778         .trcmin = 4875,
 779         .trasmin = 3500,
 780 };
 781
 782 static void ccgr_init(void)
 783 {
 784         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 785
 786         writel(0x00C03F3F, &ccm->CCGR0);
 787         writel(0x0030FC03, &ccm->CCGR1);
 788         writel(0x0FFFC000, &ccm->CCGR2);
 789         writel(0x3FF00000, &ccm->CCGR3);
 790         writel(0x00FFF300, &ccm->CCGR4);
 791         writel(0x0F0000C3, &ccm->CCGR5);
 792         writel(0x000003FF, &ccm->CCGR6);
 793 }
 794
 795 static void spl_dram_init(int width)
 796 {
 797         struct mx6_ddr_sysinfo sysinfo = {
 798                 /* width of data bus: 0=16, 1=32, 2=64 */
 799                 .dsize = width / 32,
 800                 /* config for full 4GB range so that get_mem_size() works */
 801                 .cs_density = 32,       /* 32Gb per CS */
 802                 .ncs = 1,               /* single chip select */
 803                 .cs1_mirror = 0,
 804                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 805                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 806                 .walat = 1,     /* Write additional latency */
 807                 .ralat = 5,     /* Read additional latency */
 808                 .mif3_mode = 3, /* Command prediction working mode */
 809                 .bi_on = 1,     /* Bank interleaving enabled */
 810                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 811                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 812                 .ddr_type = DDR_TYPE_DDR3,
 813                 .refsel = 1,    /* Refresh cycles at 32KHz */
 814                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 815         };
 816
 817         if (is_mx6dq())
 818                 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
 819         else
 820                 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
 821
 822         if (is_cpu_type(MXC_CPU_MX6D))
 823                 mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
 824         else if (is_cpu_type(MXC_CPU_MX6Q))
 825                 mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
 826         else if (is_cpu_type(MXC_CPU_MX6DL))
 827                 mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
 828         else if (is_cpu_type(MXC_CPU_MX6SOLO))
 829                 mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
 830 }
 831
 832 void board_init_f(ulong dummy)
 833 {
 834         /* setup AIPS and disable watchdog */
 835         arch_cpu_init();
 836
 837         ccgr_init();
 838         gpr_init();
 839
 840         /* iomux and setup of i2c */
 841         board_early_init_f();
 842
 843         /* setup GP timer */
 844         timer_init();
 845
 846         /* Enable device tree and early DM support*/
 847         spl_early_init();
 848
 849         /* UART clocks enabled and gd valid - init serial console */
 850         preloader_console_init();
 851
 852         /* DDR initialization */
 853         if (is_cpu_type(MXC_CPU_MX6SOLO))
 854                 spl_dram_init(32);
 855         else
 856                 spl_dram_init(64);
 857
 858         /* Clear the BSS. */
 859         memset(__bss_start, 0, __bss_end - __bss_start);
 860
 861         /* load/boot image from boot device */
 862         board_init_r(NULL, 0);
 863 }
 864 #endif