board/solidrun/mx6cuboxi/mx6cuboxi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   4  *
   5  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   6  *
   7  * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
   8  *
   9  * Based on SPL code from Solidrun tree, which is:
  10  * Author: Tungyi Lin <tungyilin1127@gmail.com>
  11  *
  12  * Derived from EDM_CF_IMX6 code by TechNexion,Inc
  13  * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
  14  */
  15
  16 #include <common.h>
  17 #include <image.h>
  18 #include <init.h>
  19 #include <net.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/imx-regs.h>
  22 #include <asm/arch/iomux.h>
  23 #include <asm/arch/mx6-pins.h>
  24 #include <asm/arch/mxc_hdmi.h>
  25 #include <env.h>
  26 #include <linux/errno.h>
  27 #include <asm/gpio.h>
  28 #include <asm/mach-imx/iomux-v3.h>
  29 #include <asm/mach-imx/sata.h>
  30 #include <asm/mach-imx/video.h>
  31 #include <mmc.h>
  32 #include <fsl_esdhc_imx.h>
  33 #include <malloc.h>
  34 #include <miiphy.h>
  35 #include <netdev.h>
  36 #include <asm/arch/crm_regs.h>
  37 #include <asm/io.h>
  38 #include <asm/arch/sys_proto.h>
  39 #include <spl.h>
  40 #include <usb.h>
  41 #include <usb/ehci-ci.h>
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  46         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  47         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  48
  49 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  50         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  51         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  52
  53 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  54         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  55
  56 #define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |              \
  57         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  58
  59 #define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  61
  62 #define ETH_PHY_RESET   IMX_GPIO_NR(4, 15)
  63 #define USB_H1_VBUS     IMX_GPIO_NR(1, 0)
  64
  65 enum board_type {
  66         CUBOXI          = 0x00,
  67         HUMMINGBOARD    = 0x01,
  68         HUMMINGBOARD2   = 0x02,
  69         UNKNOWN         = 0x03,
  70 };
  71
  72 static struct gpio_desc board_detect_desc[5];
  73
  74 #define MEM_STRIDE 0x4000000
  75 static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
  76 {
  77         volatile u32 *addr;
  78         u32          save[64];
  79         u32          cnt;
  80         u32          size;
  81         int          i = 0;
  82
  83         /* First save the data */
  84         for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) {
  85                 addr = (volatile u32 *)((u32)base + cnt);       /* pointer arith! */
  86                 sync ();
  87                 save[i++] = *addr;
  88                 sync ();
  89         }
  90
  91         /* First write a signature */
  92         * (volatile u32 *)base = 0x12345678;
  93         for (size = MEM_STRIDE; size < maxsize; size += MEM_STRIDE) {
  94                 * (volatile u32 *)((u32)base + size) = size;
  95                 sync ();
  96                 if (* (volatile u32 *)((u32)base) == size) {    /* We reached the overlapping address */
  97                         break;
  98                 }
  99         }
 100
 101         /* Restore the data */
 102         for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) {
 103                 addr = (volatile u32 *)((u32)base + cnt);       /* pointer arith! */
 104                 sync ();
 105                 *addr = save[i--];
 106                 sync ();
 107         }
 108
 109         return (size);
 110 }
 111
 112 int dram_init(void)
 113 {
 114         u32 max_size = imx_ddr_size();
 115
 116         gd->ram_size = get_ram_size_stride_test((u32 *) CONFIG_SYS_SDRAM_BASE,
 117                                                 (u32)max_size);
 118
 119         return 0;
 120 }
 121
 122 static iomux_v3_cfg_t const uart1_pads[] = {
 123         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 124         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 125 };
 126
 127 static iomux_v3_cfg_t const usdhc2_pads[] = {
 128         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 129         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 130         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 131         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 132         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 133         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 134 };
 135
 136 static iomux_v3_cfg_t const usdhc3_pads[] = {
 137         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 138         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 139         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 140         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 141         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 142         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 143         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 144         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 145         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 146         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 147         IOMUX_PADS(PAD_SD3_RST__SD3_RESET       | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 148 };
 149
 150 static iomux_v3_cfg_t const board_detect[] = {
 151         /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
 152         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 153         IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04   | MUX_PAD_CTRL(UART_PAD_CTRL)),
 154         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 155 };
 156
 157 static iomux_v3_cfg_t const som_rev_detect[] = {
 158         /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
 159         IOMUX_PADS(PAD_CSI0_DAT14__GPIO6_IO00  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 160         IOMUX_PADS(PAD_CSI0_DAT18__GPIO6_IO04  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 161 };
 162
 163 static void setup_iomux_uart(void)
 164 {
 165         SETUP_IOMUX_PADS(uart1_pads);
 166 }
 167
 168 static struct fsl_esdhc_cfg usdhc_cfg = {
 169         .esdhc_base = USDHC2_BASE_ADDR,
 170         .max_bus_width = 4,
 171 };
 172
 173 static struct fsl_esdhc_cfg emmc_cfg = {
 174         .esdhc_base = USDHC3_BASE_ADDR,
 175         .max_bus_width = 8,
 176 };
 177
 178 int board_mmc_get_env_dev(int devno)
 179 {
 180         return devno;
 181 }
 182
 183 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 184
 185 int board_mmc_getcd(struct mmc *mmc)
 186 {
 187         struct fsl_esdhc_cfg *cfg = mmc->priv;
 188         int ret = 0;
 189
 190         switch (cfg->esdhc_base) {
 191         case USDHC2_BASE_ADDR:
 192                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 193                 break;
 194         case USDHC3_BASE_ADDR:
 195                 ret = (mmc_get_op_cond(mmc) < 0) ? 0 : 1; /* eMMC/uSDHC3 has no CD GPIO */
 196                 break;
 197         }
 198
 199         return ret;
 200 }
 201
 202 static int mmc_init_spl(bd_t *bis)
 203 {
 204         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 205         unsigned reg = readl(&psrc->sbmr1) >> 11;
 206
 207         /*
 208          * Upon reading BOOT_CFG register the following map is done:
 209          * Bit 11 and 12 of BOOT_CFG register can determine the current
 210          * mmc port
 211          * 0x1                  SD2
 212          * 0x2                  SD3
 213          */
 214         switch (reg & 0x3) {
 215         case 0x1:
 216                 SETUP_IOMUX_PADS(usdhc2_pads);
 217                 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 218                 gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
 219                 return fsl_esdhc_initialize(bis, &usdhc_cfg);
 220         case 0x2:
 221                 SETUP_IOMUX_PADS(usdhc3_pads);
 222                 emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 223                 gd->arch.sdhc_clk = emmc_cfg.sdhc_clk;
 224                 return fsl_esdhc_initialize(bis, &emmc_cfg);
 225         }
 226
 227         return -ENODEV;
 228 }
 229
 230 int board_mmc_init(bd_t *bis)
 231 {
 232         if (IS_ENABLED(CONFIG_SPL_BUILD))
 233                 return mmc_init_spl(bis);
 234
 235         return 0;
 236 }
 237
 238 static iomux_v3_cfg_t const enet_pads[] = {
 239         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 240         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 241         /* AR8035 reset */
 242         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 243         /* AR8035 interrupt */
 244         IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 245         /* GPIO16 -> AR8035 25MHz */
 246         IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 247         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 248         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 249         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 250         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 251         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 252         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 253         /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
 254         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
 255         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 256         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 257         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 258         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 259         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 260         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 261         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 262         IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 263 };
 264
 265 static void setup_iomux_enet(void)
 266 {
 267         struct gpio_desc desc;
 268         int ret;
 269
 270         SETUP_IOMUX_PADS(enet_pads);
 271
 272         ret = dm_gpio_lookup_name("GPIO4_15", &desc);
 273         if (ret) {
 274                 printf("%s: phy reset lookup failed\n", __func__);
 275                 return;
 276         }
 277
 278         ret = dm_gpio_request(&desc, "phy-reset");
 279         if (ret) {
 280                 printf("%s: phy reset request failed\n", __func__);
 281                 return;
 282         }
 283
 284         gpio_direction_output(ETH_PHY_RESET, 0);
 285         mdelay(10);
 286         gpio_set_value(ETH_PHY_RESET, 1);
 287         udelay(100);
 288
 289         gpio_free_list_nodev(&desc, 1);
 290 }
 291
 292 int board_phy_config(struct phy_device *phydev)
 293 {
 294         if (phydev->drv->config)
 295                 phydev->drv->config(phydev);
 296
 297         return 0;
 298 }
 299
 300 /* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
 301 #define ETH_PHY_MASK    ((1 << 0x0) | (1 << 0x4))
 302
 303 int board_eth_init(bd_t *bis)
 304 {
 305         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 306         struct mii_dev *bus;
 307         struct phy_device *phydev;
 308
 309         int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
 310         if (ret)
 311                 return ret;
 312
 313         /* set gpr1[ENET_CLK_SEL] */
 314         setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 315
 316         setup_iomux_enet();
 317
 318         bus = fec_get_miibus(IMX_FEC_BASE, -1);
 319         if (!bus)
 320                 return -EINVAL;
 321
 322         phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
 323         if (!phydev) {
 324                 ret = -EINVAL;
 325                 goto free_bus;
 326         }
 327
 328         debug("using phy at address %d\n", phydev->addr);
 329         ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
 330         if (ret)
 331                 goto free_phydev;
 332
 333         return 0;
 334
 335 free_phydev:
 336         free(phydev);
 337 free_bus:
 338         free(bus);
 339         return ret;
 340 }
 341
 342 #ifdef CONFIG_VIDEO_IPUV3
 343 static void do_enable_hdmi(struct display_info_t const *dev)
 344 {
 345         imx_enable_hdmi_phy();
 346 }
 347
 348 struct display_info_t const displays[] = {
 349         {
 350                 .bus    = -1,
 351                 .addr   = 0,
 352                 .pixfmt = IPU_PIX_FMT_RGB24,
 353                 .detect = detect_hdmi,
 354                 .enable = do_enable_hdmi,
 355                 .mode   = {
 356                         .name           = "HDMI",
 357                         /* 1024x768@60Hz (VESA)*/
 358                         .refresh        = 60,
 359                         .xres           = 1024,
 360                         .yres           = 768,
 361                         .pixclock       = 15384,
 362                         .left_margin    = 160,
 363                         .right_margin   = 24,
 364                         .upper_margin   = 29,
 365                         .lower_margin   = 3,
 366                         .hsync_len      = 136,
 367                         .vsync_len      = 6,
 368                         .sync           = FB_SYNC_EXT,
 369                         .vmode          = FB_VMODE_NONINTERLACED
 370                 }
 371         }
 372 };
 373
 374 size_t display_count = ARRAY_SIZE(displays);
 375
 376 static int setup_display(void)
 377 {
 378         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 379         int reg;
 380         int timeout = 100000;
 381
 382         enable_ipu_clock();
 383         imx_setup_hdmi();
 384
 385         /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
 386         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 387
 388         reg = readl(&ccm->analog_pll_video);
 389         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 390         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
 391         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 392         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
 393         writel(reg, &ccm->analog_pll_video);
 394
 395         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 396         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 397
 398         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 399         writel(reg, &ccm->analog_pll_video);
 400
 401         while (timeout--)
 402                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 403                         break;
 404         if (timeout < 0) {
 405                 printf("Warning: video pll lock timeout!\n");
 406                 return -ETIMEDOUT;
 407         }
 408
 409         reg = readl(&ccm->analog_pll_video);
 410         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 411         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 412         writel(reg, &ccm->analog_pll_video);
 413
 414         /* gate ipu1_di0_clk */
 415         clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 416
 417         /* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
 418         reg = readl(&ccm->chsccdr);
 419         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
 420                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
 421                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 422         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
 423                (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
 424                (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 425         writel(reg, &ccm->chsccdr);
 426
 427         /* enable ipu1_di0_clk */
 428         setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 429
 430         return 0;
 431 }
 432 #endif /* CONFIG_VIDEO_IPUV3 */
 433
 434 int board_early_init_f(void)
 435 {
 436         setup_iomux_uart();
 437
 438 #ifdef CONFIG_CMD_SATA
 439         setup_sata();
 440 #endif
 441         return 0;
 442 }
 443
 444 int board_init(void)
 445 {
 446         int ret = 0;
 447
 448         /* address of boot parameters */
 449         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 450
 451 #ifdef CONFIG_VIDEO_IPUV3
 452         ret = setup_display();
 453 #endif
 454
 455         return ret;
 456 }
 457
 458 static int request_detect_gpios(void)
 459 {
 460         int node;
 461         int ret;
 462
 463         node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
 464                 "solidrun,hummingboard-detect");
 465         if (node < 0)
 466                 return -ENODEV;
 467
 468         ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
 469                 "detect-gpios", board_detect_desc,
 470                 ARRAY_SIZE(board_detect_desc), GPIOD_IS_IN);
 471
 472         return ret;
 473 }
 474
 475 static int free_detect_gpios(void)
 476 {
 477         return gpio_free_list_nodev(board_detect_desc,
 478                 ARRAY_SIZE(board_detect_desc));
 479 }
 480
 481 static enum board_type board_type(void)
 482 {
 483         int val1, val2, val3;
 484
 485         SETUP_IOMUX_PADS(board_detect);
 486
 487         /*
 488          * Machine selection -
 489          * Machine      val1, val2, val3
 490          * ----------------------------
 491          * HB2            x     x    0
 492          * HB rev 3.x     x     0    x
 493          * CBi            0     1    x
 494          * HB             1     1    x
 495          */
 496
 497         gpio_direction_input(IMX_GPIO_NR(2, 8));
 498         val3 = gpio_get_value(IMX_GPIO_NR(2, 8));
 499
 500         if (val3 == 0)
 501                 return HUMMINGBOARD2;
 502
 503         gpio_direction_input(IMX_GPIO_NR(3, 4));
 504         val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
 505
 506         if (val2 == 0)
 507                 return HUMMINGBOARD;
 508
 509         gpio_direction_input(IMX_GPIO_NR(4, 9));
 510         val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
 511
 512         if (val1 == 0) {
 513                 return CUBOXI;
 514         } else {
 515                 return HUMMINGBOARD;
 516         }
 517 }
 518
 519 static bool is_rev_15_som(void)
 520 {
 521         int val1, val2;
 522         SETUP_IOMUX_PADS(som_rev_detect);
 523
 524         val1 = gpio_get_value(IMX_GPIO_NR(6, 0));
 525         val2 = gpio_get_value(IMX_GPIO_NR(6, 4));
 526
 527         if (val1 == 1 && val2 == 0)
 528                 return true;
 529
 530         return false;
 531 }
 532
 533 static bool has_emmc(void)
 534 {
 535         struct mmc *mmc;
 536         mmc = find_mmc_device(2);
 537         if (!mmc)
 538                 return 0;
 539         return (mmc_get_op_cond(mmc) < 0) ? 0 : 1;
 540 }
 541
 542 int checkboard(void)
 543 {
 544         request_detect_gpios();
 545
 546         switch (board_type()) {
 547         case CUBOXI:
 548                 puts("Board: MX6 Cubox-i");
 549                 break;
 550         case HUMMINGBOARD:
 551                 puts("Board: MX6 HummingBoard");
 552                 break;
 553         case HUMMINGBOARD2:
 554                 puts("Board: MX6 HummingBoard2");
 555                 break;
 556         case UNKNOWN:
 557         default:
 558                 puts("Board: Unknown\n");
 559                 goto out;
 560         }
 561
 562         if (is_rev_15_som())
 563                 puts(" (som rev 1.5)\n");
 564         else
 565                 puts("\n");
 566
 567         free_detect_gpios();
 568 out:
 569         return 0;
 570 }
 571
 572 /* Override the default implementation, DT model is not accurate */
 573 int show_board_info(void)
 574 {
 575         return checkboard();
 576 }
 577
 578 int board_late_init(void)
 579 {
 580 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 581         request_detect_gpios();
 582
 583         switch (board_type()) {
 584         case CUBOXI:
 585                 env_set("board_name", "CUBOXI");
 586                 break;
 587         case HUMMINGBOARD:
 588                 env_set("board_name", "HUMMINGBOARD");
 589                 break;
 590         case HUMMINGBOARD2:
 591                 env_set("board_name", "HUMMINGBOARD2");
 592                 break;
 593         case UNKNOWN:
 594         default:
 595                 env_set("board_name", "CUBOXI");
 596         }
 597
 598         if (is_mx6dq())
 599                 env_set("board_rev", "MX6Q");
 600         else
 601                 env_set("board_rev", "MX6DL");
 602
 603         if (is_rev_15_som())
 604                 env_set("som_rev", "V15");
 605
 606         if (has_emmc())
 607                 env_set("has_emmc", "yes");
 608
 609         free_detect_gpios();
 610 #endif
 611
 612         return 0;
 613 }
 614
 615 /*
 616  * This is not a perfect match. Avoid dependency on the DM GPIO driver needed
 617  * for accurate board detection. Hummingboard2 DT is good enough for U-Boot on
 618  * all Hummingboard/Cubox-i platforms.
 619  */
 620 int board_fit_config_name_match(const char *name)
 621 {
 622         char tmp_name[36];
 623
 624         snprintf(tmp_name, sizeof(tmp_name), "%s-hummingboard2-emmc-som-v15",
 625                         is_mx6dq() ? "imx6q" : "imx6dl");
 626
 627         return strcmp(name, tmp_name);
 628 }
 629
 630 #ifdef CONFIG_SPL_BUILD
 631 #include <asm/arch/mx6-ddr.h>
 632 static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
 633         .dram_sdclk_0 =  0x00020030,
 634         .dram_sdclk_1 =  0x00020030,
 635         .dram_cas =  0x00020030,
 636         .dram_ras =  0x00020030,
 637         .dram_reset =  0x000c0030,
 638         .dram_sdcke0 =  0x00003000,
 639         .dram_sdcke1 =  0x00003000,
 640         .dram_sdba2 =  0x00000000,
 641         .dram_sdodt0 =  0x00003030,
 642         .dram_sdodt1 =  0x00003030,
 643         .dram_sdqs0 =  0x00000030,
 644         .dram_sdqs1 =  0x00000030,
 645         .dram_sdqs2 =  0x00000030,
 646         .dram_sdqs3 =  0x00000030,
 647         .dram_sdqs4 =  0x00000030,
 648         .dram_sdqs5 =  0x00000030,
 649         .dram_sdqs6 =  0x00000030,
 650         .dram_sdqs7 =  0x00000030,
 651         .dram_dqm0 =  0x00020030,
 652         .dram_dqm1 =  0x00020030,
 653         .dram_dqm2 =  0x00020030,
 654         .dram_dqm3 =  0x00020030,
 655         .dram_dqm4 =  0x00020030,
 656         .dram_dqm5 =  0x00020030,
 657         .dram_dqm6 =  0x00020030,
 658         .dram_dqm7 =  0x00020030,
 659 };
 660
 661 static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
 662         .dram_sdclk_0 = 0x00000028,
 663         .dram_sdclk_1 = 0x00000028,
 664         .dram_cas =     0x00000028,
 665         .dram_ras =     0x00000028,
 666         .dram_reset =   0x000c0028,
 667         .dram_sdcke0 =  0x00003000,
 668         .dram_sdcke1 =  0x00003000,
 669         .dram_sdba2 =   0x00000000,
 670         .dram_sdodt0 =  0x00003030,
 671         .dram_sdodt1 =  0x00003030,
 672         .dram_sdqs0 =   0x00000028,
 673         .dram_sdqs1 =   0x00000028,
 674         .dram_sdqs2 =   0x00000028,
 675         .dram_sdqs3 =   0x00000028,
 676         .dram_sdqs4 =   0x00000028,
 677         .dram_sdqs5 =   0x00000028,
 678         .dram_sdqs6 =   0x00000028,
 679         .dram_sdqs7 =   0x00000028,
 680         .dram_dqm0 =    0x00000028,
 681         .dram_dqm1 =    0x00000028,
 682         .dram_dqm2 =    0x00000028,
 683         .dram_dqm3 =    0x00000028,
 684         .dram_dqm4 =    0x00000028,
 685         .dram_dqm5 =    0x00000028,
 686         .dram_dqm6 =    0x00000028,
 687         .dram_dqm7 =    0x00000028,
 688 };
 689
 690 static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
 691         .grp_ddr_type =  0x000C0000,
 692         .grp_ddrmode_ctl =  0x00020000,
 693         .grp_ddrpke =  0x00000000,
 694         .grp_addds =  0x00000030,
 695         .grp_ctlds =  0x00000030,
 696         .grp_ddrmode =  0x00020000,
 697         .grp_b0ds =  0x00000030,
 698         .grp_b1ds =  0x00000030,
 699         .grp_b2ds =  0x00000030,
 700         .grp_b3ds =  0x00000030,
 701         .grp_b4ds =  0x00000030,
 702         .grp_b5ds =  0x00000030,
 703         .grp_b6ds =  0x00000030,
 704         .grp_b7ds =  0x00000030,
 705 };
 706
 707 static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 708         .grp_ddr_type = 0x000c0000,
 709         .grp_ddrmode_ctl = 0x00020000,
 710         .grp_ddrpke = 0x00000000,
 711         .grp_addds = 0x00000028,
 712         .grp_ctlds = 0x00000028,
 713         .grp_ddrmode = 0x00020000,
 714         .grp_b0ds = 0x00000028,
 715         .grp_b1ds = 0x00000028,
 716         .grp_b2ds = 0x00000028,
 717         .grp_b3ds = 0x00000028,
 718         .grp_b4ds = 0x00000028,
 719         .grp_b5ds = 0x00000028,
 720         .grp_b6ds = 0x00000028,
 721         .grp_b7ds = 0x00000028,
 722 };
 723
 724 /* microSOM with Dual processor and 1GB memory */
 725 static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
 726         .p0_mpwldectrl0 =  0x00000000,
 727         .p0_mpwldectrl1 =  0x00000000,
 728         .p1_mpwldectrl0 =  0x00000000,
 729         .p1_mpwldectrl1 =  0x00000000,
 730         .p0_mpdgctrl0 =    0x0314031c,
 731         .p0_mpdgctrl1 =    0x023e0304,
 732         .p1_mpdgctrl0 =    0x03240330,
 733         .p1_mpdgctrl1 =    0x03180260,
 734         .p0_mprddlctl =    0x3630323c,
 735         .p1_mprddlctl =    0x3436283a,
 736         .p0_mpwrdlctl =    0x36344038,
 737         .p1_mpwrdlctl =    0x422a423c,
 738 };
 739
 740 /* microSOM with Quad processor and 2GB memory */
 741 static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
 742         .p0_mpwldectrl0 =  0x00000000,
 743         .p0_mpwldectrl1 =  0x00000000,
 744         .p1_mpwldectrl0 =  0x00000000,
 745         .p1_mpwldectrl1 =  0x00000000,
 746         .p0_mpdgctrl0 =    0x0314031c,
 747         .p0_mpdgctrl1 =    0x023e0304,
 748         .p1_mpdgctrl0 =    0x03240330,
 749         .p1_mpdgctrl1 =    0x03180260,
 750         .p0_mprddlctl =    0x3630323c,
 751         .p1_mprddlctl =    0x3436283a,
 752         .p0_mpwrdlctl =    0x36344038,
 753         .p1_mpwrdlctl =    0x422a423c,
 754 };
 755
 756 /* microSOM with Solo processor and 512MB memory */
 757 static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
 758         .p0_mpwldectrl0 = 0x0045004D,
 759         .p0_mpwldectrl1 = 0x003A0047,
 760         .p0_mpdgctrl0 =   0x023C0224,
 761         .p0_mpdgctrl1 =   0x02000220,
 762         .p0_mprddlctl =   0x44444846,
 763         .p0_mpwrdlctl =   0x32343032,
 764 };
 765
 766 /* microSOM with Dual lite processor and 1GB memory */
 767 static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
 768         .p0_mpwldectrl0 =  0x0045004D,
 769         .p0_mpwldectrl1 =  0x003A0047,
 770         .p1_mpwldectrl0 =  0x001F001F,
 771         .p1_mpwldectrl1 =  0x00210035,
 772         .p0_mpdgctrl0 =    0x023C0224,
 773         .p0_mpdgctrl1 =    0x02000220,
 774         .p1_mpdgctrl0 =    0x02200220,
 775         .p1_mpdgctrl1 =    0x02040208,
 776         .p0_mprddlctl =    0x44444846,
 777         .p1_mprddlctl =    0x4042463C,
 778         .p0_mpwrdlctl =    0x32343032,
 779         .p1_mpwrdlctl =    0x36363430,
 780 };
 781
 782 static struct mx6_ddr3_cfg mem_ddr_2g = {
 783         .mem_speed = 1600,
 784         .density   = 2,
 785         .width     = 16,
 786         .banks     = 8,
 787         .rowaddr   = 14,
 788         .coladdr   = 10,
 789         .pagesz    = 2,
 790         .trcd      = 1375,
 791         .trcmin    = 4875,
 792         .trasmin   = 3500,
 793 };
 794
 795 static struct mx6_ddr3_cfg mem_ddr_4g = {
 796         .mem_speed = 1600,
 797         .density = 4,
 798         .width = 16,
 799         .banks = 8,
 800         .rowaddr = 16,
 801         .coladdr = 10,
 802         .pagesz = 2,
 803         .trcd = 1375,
 804         .trcmin = 4875,
 805         .trasmin = 3500,
 806 };
 807
 808 static void ccgr_init(void)
 809 {
 810         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 811
 812         writel(0x00C03F3F, &ccm->CCGR0);
 813         writel(0x0030FC03, &ccm->CCGR1);
 814         writel(0x0FFFC000, &ccm->CCGR2);
 815         writel(0x3FF00000, &ccm->CCGR3);
 816         writel(0x00FFF300, &ccm->CCGR4);
 817         writel(0x0F0000C3, &ccm->CCGR5);
 818         writel(0x000003FF, &ccm->CCGR6);
 819 }
 820
 821 static void spl_dram_init(int width)
 822 {
 823         struct mx6_ddr_sysinfo sysinfo = {
 824                 /* width of data bus: 0=16, 1=32, 2=64 */
 825                 .dsize = width / 32,
 826                 /* config for full 4GB range so that get_mem_size() works */
 827                 .cs_density = 32,       /* 32Gb per CS */
 828                 .ncs = 1,               /* single chip select */
 829                 .cs1_mirror = 0,
 830                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 831                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 832                 .walat = 1,     /* Write additional latency */
 833                 .ralat = 5,     /* Read additional latency */
 834                 .mif3_mode = 3, /* Command prediction working mode */
 835                 .bi_on = 1,     /* Bank interleaving enabled */
 836                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 837                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 838                 .ddr_type = DDR_TYPE_DDR3,
 839                 .refsel = 1,    /* Refresh cycles at 32KHz */
 840                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 841         };
 842
 843         if (is_mx6dq())
 844                 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
 845         else
 846                 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
 847
 848         if (is_cpu_type(MXC_CPU_MX6D))
 849                 mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
 850         else if (is_cpu_type(MXC_CPU_MX6Q))
 851                 mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
 852         else if (is_cpu_type(MXC_CPU_MX6DL))
 853                 mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
 854         else if (is_cpu_type(MXC_CPU_MX6SOLO))
 855                 mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
 856 }
 857
 858 void board_init_f(ulong dummy)
 859 {
 860         /* setup AIPS and disable watchdog */
 861         arch_cpu_init();
 862
 863         ccgr_init();
 864         gpr_init();
 865
 866         /* iomux and setup of i2c */
 867         board_early_init_f();
 868
 869         /* setup GP timer */
 870         timer_init();
 871
 872         /* UART clocks enabled and gd valid - init serial console */
 873         preloader_console_init();
 874
 875         /* DDR initialization */
 876         if (is_cpu_type(MXC_CPU_MX6SOLO))
 877                 spl_dram_init(32);
 878         else
 879                 spl_dram_init(64);
 880
 881         /* Clear the BSS. */
 882         memset(__bss_start, 0, __bss_end - __bss_start);
 883
 884         /* load/boot image from boot device */
 885         board_init_r(NULL, 0);
 886 }
 887 #endif