2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
8 * Based on SPL code from Solidrun tree, which is:
9 * Author: Tungyi Lin <tungyilin1127@gmail.com>
11 * Derived from EDM_CF_IMX6 code by TechNexion,Inc
12 * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
14 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/iomux.h>
20 #include <asm/arch/mx6-pins.h>
21 #include <asm/arch/mxc_hdmi.h>
22 #include <linux/errno.h>
24 #include <asm/mach-imx/iomux-v3.h>
25 #include <asm/mach-imx/sata.h>
26 #include <asm/mach-imx/video.h>
28 #include <fsl_esdhc.h>
32 #include <asm/arch/crm_regs.h>
34 #include <asm/arch/sys_proto.h>
37 #include <usb/ehci-ci.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
42 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
43 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
46 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
47 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
49 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
50 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
52 #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
53 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
55 #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
56 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
58 #define ETH_PHY_RESET IMX_GPIO_NR(4, 15)
59 #define USB_H1_VBUS IMX_GPIO_NR(1, 0)
63 gd->ram_size = imx_ddr_size();
67 static iomux_v3_cfg_t const uart1_pads[] = {
68 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
69 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
72 static iomux_v3_cfg_t const usdhc2_pads[] = {
73 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
74 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
75 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
76 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
77 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
78 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
81 static iomux_v3_cfg_t const hb_cbi_sense[] = {
82 /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
83 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(UART_PAD_CTRL)),
84 IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)),
87 static iomux_v3_cfg_t const usb_pads[] = {
88 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
91 static void setup_iomux_uart(void)
93 SETUP_IOMUX_PADS(uart1_pads);
96 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
100 int board_mmc_getcd(struct mmc *mmc)
102 return 1; /* uSDHC2 is always present */
105 int board_mmc_init(bd_t *bis)
107 SETUP_IOMUX_PADS(usdhc2_pads);
108 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
109 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
110 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
112 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
115 static iomux_v3_cfg_t const enet_pads[] = {
116 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
117 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
119 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
120 /* AR8035 interrupt */
121 IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
122 /* GPIO16 -> AR8035 25MHz */
123 IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
124 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)),
125 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
126 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
127 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
128 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
129 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
130 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
131 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
132 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
133 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
134 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
135 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
136 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
137 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
138 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
139 IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
142 static void setup_iomux_enet(void)
144 SETUP_IOMUX_PADS(enet_pads);
146 gpio_direction_output(ETH_PHY_RESET, 0);
148 gpio_set_value(ETH_PHY_RESET, 1);
152 int board_phy_config(struct phy_device *phydev)
154 if (phydev->drv->config)
155 phydev->drv->config(phydev);
160 /* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
161 #define ETH_PHY_MASK ((1 << 0x0) | (1 << 0x4))
163 int board_eth_init(bd_t *bis)
165 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
167 struct phy_device *phydev;
169 int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
173 /* set gpr1[ENET_CLK_SEL] */
174 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
178 bus = fec_get_miibus(IMX_FEC_BASE, -1);
182 phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
188 debug("using phy at address %d\n", phydev->addr);
189 ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
202 #ifdef CONFIG_VIDEO_IPUV3
203 static void do_enable_hdmi(struct display_info_t const *dev)
205 imx_enable_hdmi_phy();
208 struct display_info_t const displays[] = {
212 .pixfmt = IPU_PIX_FMT_RGB24,
213 .detect = detect_hdmi,
214 .enable = do_enable_hdmi,
217 /* 1024x768@60Hz (VESA)*/
229 .vmode = FB_VMODE_NONINTERLACED
234 size_t display_count = ARRAY_SIZE(displays);
236 static int setup_display(void)
238 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
240 int timeout = 100000;
245 /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
246 setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
248 reg = readl(&ccm->analog_pll_video);
249 reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
250 reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
251 reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
252 reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
253 writel(reg, &ccm->analog_pll_video);
255 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
256 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
258 reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
259 writel(reg, &ccm->analog_pll_video);
262 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
265 printf("Warning: video pll lock timeout!\n");
269 reg = readl(&ccm->analog_pll_video);
270 reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
271 reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
272 writel(reg, &ccm->analog_pll_video);
274 /* gate ipu1_di0_clk */
275 clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
277 /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
278 reg = readl(&ccm->chsccdr);
279 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
280 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
281 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
282 reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
283 (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
284 (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
285 writel(reg, &ccm->chsccdr);
287 /* enable ipu1_di0_clk */
288 setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
292 #endif /* CONFIG_VIDEO_IPUV3 */
294 #ifdef CONFIG_USB_EHCI_MX6
295 static void setup_usb(void)
297 SETUP_IOMUX_PADS(usb_pads);
300 int board_ehci_hcd_init(int port)
303 gpio_direction_output(USB_H1_VBUS, 1);
309 int board_early_init_f(void)
314 #ifdef CONFIG_VIDEO_IPUV3
315 ret = setup_display();
318 #ifdef CONFIG_CMD_SATA
322 #ifdef CONFIG_USB_EHCI_MX6
330 /* address of boot parameters */
331 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
336 static bool is_hummingboard(void)
340 SETUP_IOMUX_PADS(hb_cbi_sense);
342 gpio_direction_input(IMX_GPIO_NR(4, 9));
343 gpio_direction_input(IMX_GPIO_NR(3, 4));
345 val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
346 val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
349 * Machine selection -
351 * -------------------------
366 static bool is_hummingboard2(void)
370 SETUP_IOMUX_PADS(hb_cbi_sense);
372 gpio_direction_input(IMX_GPIO_NR(2, 8));
374 val1 = gpio_get_value(IMX_GPIO_NR(2, 8));
377 * Machine selection -
379 * -------------------
394 if (is_hummingboard2())
395 puts("Board: MX6 Hummingboard2\n");
396 else if (is_hummingboard())
397 puts("Board: MX6 Hummingboard\n");
399 puts("Board: MX6 Cubox-i\n");
404 int board_late_init(void)
406 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
407 if (is_hummingboard2())
408 env_set("board_name", "HUMMINGBOARD2");
409 else if (is_hummingboard())
410 env_set("board_name", "HUMMINGBOARD");
412 env_set("board_name", "CUBOXI");
415 env_set("board_rev", "MX6Q");
417 env_set("board_rev", "MX6DL");
423 #ifdef CONFIG_SPL_BUILD
424 #include <asm/arch/mx6-ddr.h>
425 static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
426 .dram_sdclk_0 = 0x00020030,
427 .dram_sdclk_1 = 0x00020030,
428 .dram_cas = 0x00020030,
429 .dram_ras = 0x00020030,
430 .dram_reset = 0x00020030,
431 .dram_sdcke0 = 0x00003000,
432 .dram_sdcke1 = 0x00003000,
433 .dram_sdba2 = 0x00000000,
434 .dram_sdodt0 = 0x00003030,
435 .dram_sdodt1 = 0x00003030,
436 .dram_sdqs0 = 0x00000030,
437 .dram_sdqs1 = 0x00000030,
438 .dram_sdqs2 = 0x00000030,
439 .dram_sdqs3 = 0x00000030,
440 .dram_sdqs4 = 0x00000030,
441 .dram_sdqs5 = 0x00000030,
442 .dram_sdqs6 = 0x00000030,
443 .dram_sdqs7 = 0x00000030,
444 .dram_dqm0 = 0x00020030,
445 .dram_dqm1 = 0x00020030,
446 .dram_dqm2 = 0x00020030,
447 .dram_dqm3 = 0x00020030,
448 .dram_dqm4 = 0x00020030,
449 .dram_dqm5 = 0x00020030,
450 .dram_dqm6 = 0x00020030,
451 .dram_dqm7 = 0x00020030,
454 static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
455 .dram_sdclk_0 = 0x00000028,
456 .dram_sdclk_1 = 0x00000028,
457 .dram_cas = 0x00000028,
458 .dram_ras = 0x00000028,
459 .dram_reset = 0x000c0028,
460 .dram_sdcke0 = 0x00003000,
461 .dram_sdcke1 = 0x00003000,
462 .dram_sdba2 = 0x00000000,
463 .dram_sdodt0 = 0x00003030,
464 .dram_sdodt1 = 0x00003030,
465 .dram_sdqs0 = 0x00000028,
466 .dram_sdqs1 = 0x00000028,
467 .dram_sdqs2 = 0x00000028,
468 .dram_sdqs3 = 0x00000028,
469 .dram_sdqs4 = 0x00000028,
470 .dram_sdqs5 = 0x00000028,
471 .dram_sdqs6 = 0x00000028,
472 .dram_sdqs7 = 0x00000028,
473 .dram_dqm0 = 0x00000028,
474 .dram_dqm1 = 0x00000028,
475 .dram_dqm2 = 0x00000028,
476 .dram_dqm3 = 0x00000028,
477 .dram_dqm4 = 0x00000028,
478 .dram_dqm5 = 0x00000028,
479 .dram_dqm6 = 0x00000028,
480 .dram_dqm7 = 0x00000028,
483 static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
484 .grp_ddr_type = 0x000C0000,
485 .grp_ddrmode_ctl = 0x00020000,
486 .grp_ddrpke = 0x00000000,
487 .grp_addds = 0x00000030,
488 .grp_ctlds = 0x00000030,
489 .grp_ddrmode = 0x00020000,
490 .grp_b0ds = 0x00000030,
491 .grp_b1ds = 0x00000030,
492 .grp_b2ds = 0x00000030,
493 .grp_b3ds = 0x00000030,
494 .grp_b4ds = 0x00000030,
495 .grp_b5ds = 0x00000030,
496 .grp_b6ds = 0x00000030,
497 .grp_b7ds = 0x00000030,
500 static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
501 .grp_ddr_type = 0x000c0000,
502 .grp_ddrmode_ctl = 0x00020000,
503 .grp_ddrpke = 0x00000000,
504 .grp_addds = 0x00000028,
505 .grp_ctlds = 0x00000028,
506 .grp_ddrmode = 0x00020000,
507 .grp_b0ds = 0x00000028,
508 .grp_b1ds = 0x00000028,
509 .grp_b2ds = 0x00000028,
510 .grp_b3ds = 0x00000028,
511 .grp_b4ds = 0x00000028,
512 .grp_b5ds = 0x00000028,
513 .grp_b6ds = 0x00000028,
514 .grp_b7ds = 0x00000028,
517 /* microSOM with Dual processor and 1GB memory */
518 static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
519 .p0_mpwldectrl0 = 0x00000000,
520 .p0_mpwldectrl1 = 0x00000000,
521 .p1_mpwldectrl0 = 0x00000000,
522 .p1_mpwldectrl1 = 0x00000000,
523 .p0_mpdgctrl0 = 0x0314031c,
524 .p0_mpdgctrl1 = 0x023e0304,
525 .p1_mpdgctrl0 = 0x03240330,
526 .p1_mpdgctrl1 = 0x03180260,
527 .p0_mprddlctl = 0x3630323c,
528 .p1_mprddlctl = 0x3436283a,
529 .p0_mpwrdlctl = 0x36344038,
530 .p1_mpwrdlctl = 0x422a423c,
533 /* microSOM with Quad processor and 2GB memory */
534 static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
535 .p0_mpwldectrl0 = 0x00000000,
536 .p0_mpwldectrl1 = 0x00000000,
537 .p1_mpwldectrl0 = 0x00000000,
538 .p1_mpwldectrl1 = 0x00000000,
539 .p0_mpdgctrl0 = 0x0314031c,
540 .p0_mpdgctrl1 = 0x023e0304,
541 .p1_mpdgctrl0 = 0x03240330,
542 .p1_mpdgctrl1 = 0x03180260,
543 .p0_mprddlctl = 0x3630323c,
544 .p1_mprddlctl = 0x3436283a,
545 .p0_mpwrdlctl = 0x36344038,
546 .p1_mpwrdlctl = 0x422a423c,
549 /* microSOM with Solo processor and 512MB memory */
550 static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
551 .p0_mpwldectrl0 = 0x0045004D,
552 .p0_mpwldectrl1 = 0x003A0047,
553 .p0_mpdgctrl0 = 0x023C0224,
554 .p0_mpdgctrl1 = 0x02000220,
555 .p0_mprddlctl = 0x44444846,
556 .p0_mpwrdlctl = 0x32343032,
559 /* microSOM with Dual lite processor and 1GB memory */
560 static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
561 .p0_mpwldectrl0 = 0x0045004D,
562 .p0_mpwldectrl1 = 0x003A0047,
563 .p1_mpwldectrl0 = 0x001F001F,
564 .p1_mpwldectrl1 = 0x00210035,
565 .p0_mpdgctrl0 = 0x023C0224,
566 .p0_mpdgctrl1 = 0x02000220,
567 .p1_mpdgctrl0 = 0x02200220,
568 .p1_mpdgctrl1 = 0x02040208,
569 .p0_mprddlctl = 0x44444846,
570 .p1_mprddlctl = 0x4042463C,
571 .p0_mpwrdlctl = 0x32343032,
572 .p1_mpwrdlctl = 0x36363430,
575 static struct mx6_ddr3_cfg mem_ddr_2g = {
589 static struct mx6_ddr3_cfg mem_ddr_4g = {
602 static void ccgr_init(void)
604 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
606 writel(0x00C03F3F, &ccm->CCGR0);
607 writel(0x0030FC03, &ccm->CCGR1);
608 writel(0x0FFFC000, &ccm->CCGR2);
609 writel(0x3FF00000, &ccm->CCGR3);
610 writel(0x00FFF300, &ccm->CCGR4);
611 writel(0x0F0000C3, &ccm->CCGR5);
612 writel(0x000003FF, &ccm->CCGR6);
615 static void spl_dram_init(int width)
617 struct mx6_ddr_sysinfo sysinfo = {
618 /* width of data bus: 0=16, 1=32, 2=64 */
620 /* config for full 4GB range so that get_mem_size() works */
621 .cs_density = 32, /* 32Gb per CS */
622 .ncs = 1, /* single chip select */
624 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
625 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
626 .walat = 1, /* Write additional latency */
627 .ralat = 5, /* Read additional latency */
628 .mif3_mode = 3, /* Command prediction working mode */
629 .bi_on = 1, /* Bank interleaving enabled */
630 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
631 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
632 .ddr_type = DDR_TYPE_DDR3,
633 .refsel = 1, /* Refresh cycles at 32KHz */
634 .refr = 7, /* 8 refresh commands per refresh cycle */
638 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
640 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
642 if (is_cpu_type(MXC_CPU_MX6D))
643 mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
644 else if (is_cpu_type(MXC_CPU_MX6Q))
645 mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
646 else if (is_cpu_type(MXC_CPU_MX6DL))
647 mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
648 else if (is_cpu_type(MXC_CPU_MX6SOLO))
649 mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
652 void board_init_f(ulong dummy)
654 /* setup AIPS and disable watchdog */
660 /* iomux and setup of i2c */
661 board_early_init_f();
666 /* UART clocks enabled and gd valid - init serial console */
667 preloader_console_init();
669 /* DDR initialization */
670 if (is_cpu_type(MXC_CPU_MX6SOLO))
676 memset(__bss_start, 0, __bss_end - __bss_start);
678 /* load/boot image from boot device */
679 board_init_r(NULL, 0);