1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/soc.h>
16 #include <linux/bitops.h>
17 #include <linux/delay.h>
18 #include "../common/tlv_data.h"
20 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
21 #include <../serdes/a38x/high_speed_env_spec.h>
23 DECLARE_GLOBAL_DATA_PTR;
26 * Those values and defines are taken from the Marvell U-Boot version
27 * "u-boot-2013.01-15t1-clearfog"
29 #define BOARD_GPP_OUT_ENA_LOW 0xffffffff
30 #define BOARD_GPP_OUT_ENA_MID 0xffffffff
32 #define BOARD_GPP_OUT_VAL_LOW 0x0
33 #define BOARD_GPP_OUT_VAL_MID 0x0
34 #define BOARD_GPP_POL_LOW 0x0
35 #define BOARD_GPP_POL_MID 0x0
37 static struct tlv_data cf_tlv_data;
39 static void cf_read_tlv_data(void)
41 static bool read_once;
47 read_tlv_data(&cf_tlv_data);
50 /* The starting board_serdes_map reflects original Clearfog Pro usage */
51 static struct serdes_map board_serdes_map[] = {
52 {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
53 {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
54 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
55 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
56 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
57 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
60 void config_cfbase_serdes_map(void)
62 board_serdes_map[4].serdes_type = USB3_HOST0;
63 board_serdes_map[4].serdes_speed = SERDES_SPEED_5_GBPS;
64 board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
67 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
71 /* Apply build configuration options before runtime configuration */
72 if (IS_ENABLED(CONFIG_CLEARFOG_SFP_25GB))
73 board_serdes_map[5].serdes_speed = SERDES_SPEED_3_125_GBPS;
75 if (IS_ENABLED(CONFIG_CLEARFOG_CON2_SATA)) {
76 board_serdes_map[4].serdes_type = SATA2;
77 board_serdes_map[4].serdes_speed = SERDES_SPEED_3_GBPS;
78 board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
79 board_serdes_map[4].swap_rx = 1;
82 if (IS_ENABLED(CONFIG_CLEARFOG_CON3_SATA)) {
83 board_serdes_map[2].serdes_type = SATA1;
84 board_serdes_map[2].serdes_speed = SERDES_SPEED_3_GBPS;
85 board_serdes_map[2].serdes_mode = SERDES_DEFAULT_MODE;
86 board_serdes_map[2].swap_rx = 1;
89 /* Apply runtime detection changes */
90 if (sr_product_is(&cf_tlv_data, "Clearfog GTR")) {
91 board_serdes_map[0].serdes_type = PEX0;
92 board_serdes_map[0].serdes_speed = SERDES_SPEED_5_GBPS;
93 board_serdes_map[0].serdes_mode = PEX_ROOT_COMPLEX_X1;
94 } else if (sr_product_is(&cf_tlv_data, "Clearfog Pro")) {
95 /* handle recognized product as noop, no adjustment required */
96 } else if (sr_product_is(&cf_tlv_data, "Clearfog Base")) {
97 config_cfbase_serdes_map();
100 * Fallback to static default. EEPROM TLV support is not
101 * enabled, runtime detection failed, hardware support is not
102 * present, EEPROM is corrupt, or an unrecognized product name
105 if (IS_ENABLED(CONFIG_SPL_CMD_TLV_EEPROM))
106 puts("EEPROM TLV detection failed: ");
107 puts("Using static config for ");
108 if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE)) {
109 puts("Clearfog Base.\n");
110 config_cfbase_serdes_map();
112 puts("Clearfog Pro.\n");
116 *serdes_map_array = board_serdes_map;
117 *count = ARRAY_SIZE(board_serdes_map);
122 * Define the DDR layout / topology here in the board file. This will
123 * be used by the DDR3 init code in the SPL U-Boot version to configure
124 * the DDR3 controller.
126 static struct mv_ddr_topology_map board_topology_map = {
128 0x1, /* active interfaces */
129 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
130 { { { {0x1, 0, 0, 0},
135 SPEED_BIN_DDR_1600K, /* speed_bin */
136 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
137 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
138 MV_DDR_FREQ_800, /* frequency */
139 0, 0, /* cas_wl cas_l */
140 MV_DDR_TEMP_LOW, /* temperature */
141 MV_DDR_TIM_DEFAULT} }, /* timing */
142 BUS_MASK_32BIT, /* Busses mask */
143 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
144 { {0} }, /* raw spd data */
145 {0}, /* timing parameters */
146 { {0} }, /* electrical configuration */
147 {0,}, /* electrical parameters */
148 0x3, /* clock enable mask */
151 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
153 struct if_params *ifp = &board_topology_map.interface_params[0];
157 switch (cf_tlv_data.ram_size) {
160 ifp->memory_size = MV_DDR_DIE_CAP_4GBIT;
163 ifp->memory_size = MV_DDR_DIE_CAP_8GBIT;
167 /* Return the board topology as defined in the board code */
168 return &board_topology_map;
171 int board_early_init_f(void)
174 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
175 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
176 writel(0x10400011, MVEBU_MPP_BASE + 0x08);
177 writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
178 writel(0x44400002, MVEBU_MPP_BASE + 0x10);
179 writel(0x41144004, MVEBU_MPP_BASE + 0x14);
180 writel(0x40333333, MVEBU_MPP_BASE + 0x18);
181 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
183 /* Set GPP Out value */
184 writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
185 writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
187 /* Set GPP Polarity */
188 writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
189 writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
191 /* Set GPP Out Enable */
192 writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
193 writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
200 /* Address of boot parameters */
201 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
203 /* Toggle GPIO41 to reset onboard switch and phy */
204 clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
205 clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
206 /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
207 clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
208 clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
210 setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
211 setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
219 char *board = "Clearfog Pro";
220 if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE))
221 board = "Clearfog Base";
224 if (strlen(cf_tlv_data.tlv_product_name[0]) > 0)
225 board = cf_tlv_data.tlv_product_name[0];
227 printf("Board: SolidRun %s", board);
228 if (strlen(cf_tlv_data.tlv_product_name[1]) > 0)
229 printf(", %s", cf_tlv_data.tlv_product_name[1]);
235 int board_eth_init(bd_t *bis)
237 cpu_eth_init(bis); /* Built in controller(s) come first */
238 return pci_eth_init(bis);
241 int board_late_init(void)
245 if (sr_product_is(&cf_tlv_data, "Clearfog Base"))
246 env_set("fdtfile", "armada-388-clearfog-base.dtb");
247 else if (sr_product_is(&cf_tlv_data, "Clearfog GTR S4"))
248 env_set("fdtfile", "armada-385-clearfog-gtr-s4.dtb");
249 else if (sr_product_is(&cf_tlv_data, "Clearfog GTR L8"))
250 env_set("fdtfile", "armada-385-clearfog-gtr-l8.dtb");
251 else if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE))
252 env_set("fdtfile", "armada-388-clearfog-base.dtb");
254 env_set("fdtfile", "armada-388-clearfog-pro.dtb");