1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * Altera SoCFPGA Clock and PLL configuration
6 #ifndef __SOCFPGA_PLL_CONFIG_H__
7 #define __SOCFPGA_PLL_CONFIG_H__
9 #define CFG_HPS_DBCTRL_STAYOSC1 1
11 #define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
12 #define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
13 #define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
14 #define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
15 #define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
16 #define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
17 #define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
18 #define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
19 #define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
20 #define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
21 #define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
22 #define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
23 #define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
24 #define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
25 #define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
26 #define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
27 #define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
29 #define CFG_HPS_PERPLLGRP_VCO_DENOM 0
30 #define CFG_HPS_PERPLLGRP_VCO_NUMER 39
31 #define CFG_HPS_PERPLLGRP_VCO_PSRC 0
32 #define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
33 #define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
34 #define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
35 #define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
36 #define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
37 #define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
38 #define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
39 #define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
40 #define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
41 #define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
42 #define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
43 #define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
44 #define CFG_HPS_PERPLLGRP_SRC_NAND 2
45 #define CFG_HPS_PERPLLGRP_SRC_QSPI 1
47 #define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
48 #define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
49 #define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
50 #define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
51 #define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
52 #define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
53 #define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
54 #define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
55 #define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
56 #define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
57 #define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
59 #define CFG_HPS_CLK_OSC1_HZ 25000000
60 #define CFG_HPS_CLK_OSC2_HZ 25000000
61 #define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
62 #define CFG_HPS_CLK_F2S_PER_REF_HZ 0
63 #define CFG_HPS_CLK_MAINVCO_HZ 1600000000
64 #define CFG_HPS_CLK_PERVCO_HZ 1000000000
65 #define CFG_HPS_CLK_SDRVCO_HZ 800000000
66 #define CFG_HPS_CLK_EMAC0_HZ 250000000
67 #define CFG_HPS_CLK_EMAC1_HZ 250000000
68 #define CFG_HPS_CLK_USBCLK_HZ 200000000
69 #define CFG_HPS_CLK_NAND_HZ 488281
70 #define CFG_HPS_CLK_SDMMC_HZ 1953125
71 #define CFG_HPS_CLK_QSPI_HZ 320000000
72 #define CFG_HPS_CLK_SPIM_HZ 200000000
73 #define CFG_HPS_CLK_CAN0_HZ 12500000
74 #define CFG_HPS_CLK_CAN1_HZ 12500000
75 #define CFG_HPS_CLK_GPIODB_HZ 32000
76 #define CFG_HPS_CLK_L4_MP_HZ 100000000
77 #define CFG_HPS_CLK_L4_SP_HZ 100000000
79 #define CFG_HPS_ALTERAGRP_MPUCLK 1
80 #define CFG_HPS_ALTERAGRP_MAINCLK 3
81 #define CFG_HPS_ALTERAGRP_DBGATCLK 3
84 #endif /* __SOCFPGA_PLL_CONFIG_H__ */