board/softing/vining_2000/vining_2000.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 samtec automotive software & electronics gmbh
   4  * Copyright (C) 2017-2019 softing automotive electronics gmbH
   5  *
   6  * Author: Christoph Fritz <chf.fritz@googlemail.com>
   7  */
   8
   9 #include <init.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/io.h>
  19 #include <asm/mach-imx/mxc_i2c.h>
  20 #include <env.h>
  21 #include <linux/sizes.h>
  22 #include <common.h>
  23 #include <fsl_esdhc_imx.h>
  24 #include <mmc.h>
  25 #include <i2c.h>
  26 #include <miiphy.h>
  27 #include <netdev.h>
  28 #include <power/pmic.h>
  29 #include <power/pfuze100_pmic.h>
  30 #include <usb.h>
  31 #include <usb/ehci-ci.h>
  32 #include <pwm.h>
  33 #include <wait_bit.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #define UART_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |     \
  38         PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |   \
  39         PAD_CTL_SRE_FAST)
  40
  41 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE |     \
  42         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm |                \
  43         PAD_CTL_SRE_FAST)
  44
  45 #define ENET_CLK_PAD_CTRL  PAD_CTL_DSE_34ohm
  46
  47 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE |                        \
  48         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH |            \
  49         PAD_CTL_SRE_FAST)
  50
  51 #define I2C_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |      \
  52         PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED |         \
  53         PAD_CTL_DSE_40ohm)
  54
  55 #define USDHC_CLK_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_SPEED_MED |  \
  56         PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
  57
  58 #define USDHC_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP |     \
  59         PAD_CTL_PKE |  PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm |  \
  60         PAD_CTL_SRE_FAST)
  61
  62 #define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP |    \
  63         PAD_CTL_PKE |  PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)
  64
  65 #define GPIO_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |     \
  66         PAD_CTL_PKE)
  67
  68 int dram_init(void)
  69 {
  70         gd->ram_size = imx_ddr_size();
  71
  72         return 0;
  73 }
  74
  75 static iomux_v3_cfg_t const fec1_pads[] = {
  76         MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  77         MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  78         MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  79         MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  80         MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  81         MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82         MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  83         MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) |
  85                 MUX_MODE_SION,
  86         /* LAN8720 PHY Reset */
  87         MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
  88 };
  89
  90 static iomux_v3_cfg_t const pwm_led_pads[] = {
  91         MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
  92         MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
  93         MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
  94 };
  95
  96 #define PHY_RESET IMX_GPIO_NR(5, 9)
  97
  98 int board_eth_init(bd_t *bis)
  99 {
 100         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 101         int ret;
 102         unsigned char eth1addr[6];
 103
 104         /* just to get secound mac address */
 105         imx_get_mac_from_fuse(1, eth1addr);
 106         if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
 107                 eth_env_set_enetaddr("eth1addr", eth1addr);
 108
 109         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 110
 111         /*
 112          * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
 113          * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
 114          * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
 115          */
 116         clrsetbits_le32(&iomuxc_regs->gpr[1],
 117                         IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
 118                         IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
 119                         IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
 120                         IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
 121
 122         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 123         if (ret)
 124                 goto eth_fail;
 125
 126         /* reset phy */
 127         gpio_request(PHY_RESET, "PHY-reset");
 128         gpio_direction_output(PHY_RESET, 0);
 129         mdelay(16);
 130         gpio_set_value(PHY_RESET, 1);
 131         mdelay(1);
 132
 133         ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
 134                                         IMX_FEC_BASE);
 135         if (ret)
 136                 goto eth_fail;
 137
 138         return ret;
 139
 140 eth_fail:
 141         printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
 142         gpio_set_value(PHY_RESET, 0);
 143         return ret;
 144 }
 145
 146 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 147 /* I2C1 for PMIC */
 148 static struct i2c_pads_info i2c_pad_info1 = {
 149         .scl = {
 150                 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
 151                 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
 152                 .gp = IMX_GPIO_NR(1, 0),
 153         },
 154         .sda = {
 155                 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
 156                 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
 157                 .gp = IMX_GPIO_NR(1, 1),
 158         },
 159 };
 160
 161 static struct pmic *pfuze_init(unsigned char i2cbus)
 162 {
 163         struct pmic *p;
 164         int ret;
 165         u32 reg;
 166
 167         ret = power_pfuze100_init(i2cbus);
 168         if (ret)
 169                 return NULL;
 170
 171         p = pmic_get("PFUZE100");
 172         ret = pmic_probe(p);
 173         if (ret)
 174                 return NULL;
 175
 176         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 177         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 178
 179         /* Set SW1AB stanby volage to 0.975V */
 180         pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 181         reg &= ~SW1x_STBY_MASK;
 182         reg |= SW1x_0_975V;
 183         pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
 184
 185         /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 186         pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
 187         reg &= ~SW1xCONF_DVSSPEED_MASK;
 188         reg |= SW1xCONF_DVSSPEED_4US;
 189         pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
 190
 191         /* Set SW1C standby voltage to 0.975V */
 192         pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
 193         reg &= ~SW1x_STBY_MASK;
 194         reg |= SW1x_0_975V;
 195         pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
 196
 197         /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
 198         pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
 199         reg &= ~SW1xCONF_DVSSPEED_MASK;
 200         reg |= SW1xCONF_DVSSPEED_4US;
 201         pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
 202
 203         return p;
 204 }
 205
 206 static int pfuze_mode_init(struct pmic *p, u32 mode)
 207 {
 208         unsigned char offset, i, switch_num;
 209         u32 id;
 210         int ret;
 211
 212         pmic_reg_read(p, PFUZE100_DEVICEID, &id);
 213         id = id & 0xf;
 214
 215         if (id == 0) {
 216                 switch_num = 6;
 217                 offset = PFUZE100_SW1CMODE;
 218         } else if (id == 1) {
 219                 switch_num = 4;
 220                 offset = PFUZE100_SW2MODE;
 221         } else {
 222                 printf("Not supported, id=%d\n", id);
 223                 return -EINVAL;
 224         }
 225
 226         ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
 227         if (ret < 0) {
 228                 printf("Set SW1AB mode error!\n");
 229                 return ret;
 230         }
 231
 232         for (i = 0; i < switch_num - 1; i++) {
 233                 ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
 234                 if (ret < 0) {
 235                         printf("Set switch 0x%x mode error!\n",
 236                                offset + i * SWITCH_SIZE);
 237                         return ret;
 238                 }
 239         }
 240
 241         return ret;
 242 }
 243
 244 int power_init_board(void)
 245 {
 246         struct pmic *p;
 247         int ret;
 248
 249         p = pfuze_init(I2C_PMIC);
 250         if (!p)
 251                 return -ENODEV;
 252
 253         ret = pfuze_mode_init(p, APS_PFM);
 254         if (ret < 0)
 255                 return ret;
 256
 257         return 0;
 258 }
 259
 260 #ifdef CONFIG_USB_EHCI_MX6
 261 static iomux_v3_cfg_t const usb_otg_pads[] = {
 262         /* OGT1 */
 263         MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 264         MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
 265         /* OTG2 */
 266         MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
 267 };
 268
 269 static void setup_iomux_usb(void)
 270 {
 271         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 272                                          ARRAY_SIZE(usb_otg_pads));
 273 }
 274
 275 int board_usb_phy_mode(int port)
 276 {
 277         if (port == 1)
 278                 return USB_INIT_HOST;
 279         else
 280                 return usb_phy_mode(port);
 281 }
 282 #endif
 283
 284 #ifdef CONFIG_PWM_IMX
 285 static int set_pwm_leds(void)
 286 {
 287         int ret;
 288
 289         imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
 290                                          ARRAY_SIZE(pwm_led_pads));
 291         /* enable backlight PWM 2, green LED */
 292         ret = pwm_init(1, 0, 0);
 293         if (ret)
 294                 goto error;
 295         /* duty cycle 200ns, period: 8000ns */
 296         ret = pwm_config(1, 200, 8000);
 297         if (ret)
 298                 goto error;
 299         ret = pwm_enable(1);
 300         if (ret)
 301                 goto error;
 302
 303         /* enable backlight PWM 1, blue LED */
 304         ret = pwm_init(0, 0, 0);
 305         if (ret)
 306                 goto error;
 307         /* duty cycle 200ns, period: 8000ns */
 308         ret = pwm_config(0, 200, 8000);
 309         if (ret)
 310                 goto error;
 311         ret = pwm_enable(0);
 312         if (ret)
 313                 goto error;
 314
 315         /* enable backlight PWM 6, red LED */
 316         ret = pwm_init(5, 0, 0);
 317         if (ret)
 318                 goto error;
 319         /* duty cycle 200ns, period: 8000ns */
 320         ret = pwm_config(5, 200, 8000);
 321         if (ret)
 322                 goto error;
 323         ret = pwm_enable(5);
 324
 325 error:
 326         return ret;
 327 }
 328 #else
 329 static int set_pwm_leds(void)
 330 {
 331         return 0;
 332 }
 333 #endif
 334
 335 #define ADCx_HC0        0x00
 336 #define ADCx_HS         0x08
 337 #define ADCx_HS_C0      BIT(0)
 338 #define ADCx_R0         0x0c
 339 #define ADCx_CFG        0x14
 340 #define ADCx_CFG_SWMODE 0x308
 341 #define ADCx_GC         0x18
 342 #define ADCx_GC_CAL     BIT(7)
 343
 344 static int read_adc(u32 *val)
 345 {
 346         int ret;
 347         void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
 348
 349         /* use software mode */
 350         writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
 351
 352         /* start auto calibration */
 353         setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
 354         ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
 355         if (ret)
 356                 goto adc_exit;
 357
 358         /* start conversion */
 359         writel(0, b + ADCx_HC0);
 360
 361         /* wait for conversion */
 362         ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
 363         if (ret)
 364                 goto adc_exit;
 365
 366         /* read result */
 367         *val = readl(b + ADCx_R0);
 368
 369 adc_exit:
 370         if (ret)
 371                 printf("ADC failure (ret=%i)\n", ret);
 372         unmap_physmem(b, MAP_NOCACHE);
 373         return ret;
 374 }
 375
 376 #define VAL_UPPER       2498
 377 #define VAL_LOWER       1550
 378
 379 static int set_pin_state(void)
 380 {
 381         u32 val;
 382         int ret;
 383
 384         ret = read_adc(&val);
 385         if (ret)
 386                 return ret;
 387
 388         if (val >= VAL_UPPER)
 389                 env_set("pin_state", "connected");
 390         else if (val < VAL_UPPER && val > VAL_LOWER)
 391                 env_set("pin_state", "open");
 392         else
 393                 env_set("pin_state", "button");
 394
 395         return ret;
 396 }
 397
 398 int board_late_init(void)
 399 {
 400         int ret;
 401
 402         ret = set_pwm_leds();
 403         if (ret)
 404                 return ret;
 405
 406         ret = set_pin_state();
 407
 408         return ret;
 409 }
 410
 411 int board_early_init_f(void)
 412 {
 413         setup_iomux_usb();
 414
 415         return 0;
 416 }
 417
 418 int board_init(void)
 419 {
 420         /* Address of boot parameters */
 421         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 422
 423 #ifdef CONFIG_SYS_I2C_MXC
 424         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 425 #endif
 426
 427         return 0;
 428 }
 429
 430 int checkboard(void)
 431 {
 432         puts("Board: VIN|ING 2000\n");
 433
 434         return 0;
 435 }
 436
 437 #ifdef CONFIG_SPL_BUILD
 438 #include <linux/libfdt.h>
 439 #include <spl.h>
 440 #include <asm/arch/mx6-ddr.h>
 441
 442 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
 443
 444 static iomux_v3_cfg_t const uart_pads[] = {
 445         MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 446         MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 447 };
 448
 449 static iomux_v3_cfg_t const usdhc4_pads[] = {
 450         MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 451         MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 452         MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 453         MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 454         MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 455         MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 456         MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 457         MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 458         MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 459         MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 460 };
 461
 462 static void vining2000_spl_setup_iomux_uart(void)
 463 {
 464         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 465 }
 466
 467 int board_mmc_init(bd_t *bis)
 468 {
 469         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 470         u32 val;
 471         u32 port;
 472
 473         val = readl(&src_regs->sbmr1);
 474
 475         if ((val & 0xc0) != 0x40) {
 476                 printf("Not boot from USDHC!\n");
 477                 return -EINVAL;
 478         }
 479
 480         port = (val >> 11) & 0x3;
 481         printf("port %d\n", port);
 482         switch (port) {
 483         case 3:
 484                 imx_iomux_v3_setup_multiple_pads(
 485                         usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 486                 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 487                 usdhc_cfg.esdhc_base = USDHC4_BASE_ADDR;
 488                 break;
 489         }
 490
 491         gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
 492         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 493 }
 494
 495 int board_mmc_getcd(struct mmc *mmc)
 496 {
 497         return 1;
 498 }
 499
 500 const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
 501         .dram_dqm0              = 0x00000028,
 502         .dram_dqm1              = 0x00000028,
 503         .dram_dqm2              = 0x00000028,
 504         .dram_dqm3              = 0x00000028,
 505         .dram_ras               = 0x00000028,
 506         .dram_cas               = 0x00000028,
 507         .dram_odt0              = 0x00000028,
 508         .dram_odt1              = 0x00000028,
 509         .dram_sdba2             = 0x00000000,
 510         .dram_sdcke0            = 0x00003000,
 511         .dram_sdcke1            = 0x00003000,
 512         .dram_sdclk_0           = 0x00000030,
 513         .dram_sdqs0             = 0x00000028,
 514         .dram_sdqs1             = 0x00000028,
 515         .dram_sdqs2             = 0x00000028,
 516         .dram_sdqs3             = 0x00000028,
 517         .dram_reset             = 0x00000028,
 518 };
 519
 520 const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
 521         .grp_addds              = 0x00000028,
 522         .grp_b0ds               = 0x00000028,
 523         .grp_b1ds               = 0x00000028,
 524         .grp_b2ds               = 0x00000028,
 525         .grp_b3ds               = 0x00000028,
 526         .grp_ctlds              = 0x00000028,
 527         .grp_ddr_type           = 0x000c0000,
 528         .grp_ddrmode            = 0x00020000,
 529         .grp_ddrmode_ctl        = 0x00020000,
 530         .grp_ddrpke             = 0x00000000,
 531 };
 532
 533 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
 534         .p0_mpwldectrl0         = 0x0022001C,
 535         .p0_mpwldectrl1         = 0x001F001A,
 536         .p0_mpdgctrl0           = 0x01380134,
 537         .p0_mpdgctrl1           = 0x0124011C,
 538         .p0_mprddlctl           = 0x42404444,
 539         .p0_mpwrdlctl           = 0x36383C38,
 540 };
 541
 542 static struct mx6_ddr3_cfg mem_ddr = {
 543         .mem_speed      = 1600,
 544         .density        = 4,
 545         .width          = 32,
 546         .banks          = 8,
 547         .rowaddr        = 15,
 548         .coladdr        = 10,
 549         .pagesz         = 2,
 550         .trcd           = 1391,
 551         .trcmin         = 4875,
 552         .trasmin        = 3500,
 553 };
 554
 555 static void ccgr_init(void)
 556 {
 557         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 558
 559         writel(0xF000000F, &ccm->CCGR0);        /* AIPS_TZ{1,2,3} */
 560         writel(0x303C0000, &ccm->CCGR1);        /* GPT, OCRAM */
 561         writel(0x00FFFCC0, &ccm->CCGR2);        /* IPMUX, I2C1, I2C3 */
 562         writel(0x3F300030, &ccm->CCGR3);        /* OCRAM, MMDC, ENET */
 563         writel(0x0000C003, &ccm->CCGR4);        /* PCI, PL301 */
 564         writel(0x0F0330C3, &ccm->CCGR5);        /* UART, ROM */
 565         writel(0x00000F00, &ccm->CCGR6);        /* SDHI4, EIM */
 566 }
 567
 568 static void vining2000_spl_dram_init(void)
 569 {
 570         struct mx6_ddr_sysinfo sysinfo = {
 571                 .dsize          = mem_ddr.width / 32,
 572                 .cs_density     = 24,
 573                 .ncs            = 1,
 574                 .cs1_mirror     = 0,
 575                 .rtt_wr         = 1,    /* RTT_wr = RZQ/4 */
 576                 .rtt_nom        = 1,    /* RTT_Nom = RZQ/4 */
 577                 .walat          = 1,    /* Write additional latency */
 578                 .ralat          = 5,    /* Read additional latency */
 579                 .mif3_mode      = 3,    /* Command prediction working mode */
 580                 .bi_on          = 1,    /* Bank interleaving enabled */
 581                 .sde_to_rst     = 0x10, /* 14 cycles, 200us (JEDEC default) */
 582                 .rst_to_cke     = 0x23, /* 33 cycles, 500us (JEDEC default) */
 583                 .ddr_type       = DDR_TYPE_DDR3,
 584                 .refsel         = 1,    /* Refresh cycles at 32KHz */
 585                 .refr           = 7,    /* 8 refresh commands per refresh cycle */
 586         };
 587
 588         mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 589         mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
 590
 591         /* Perform DDR DRAM calibration */
 592         udelay(100);
 593         mmdc_do_write_level_calibration(&sysinfo);
 594         mmdc_do_dqs_calibration(&sysinfo);
 595 }
 596
 597 void board_init_f(ulong dummy)
 598 {
 599         /* setup AIPS and disable watchdog */
 600         arch_cpu_init();
 601
 602         ccgr_init();
 603
 604         /* iomux setup */
 605         vining2000_spl_setup_iomux_uart();
 606
 607         /* setup GP timer */
 608         timer_init();
 609
 610         /* UART clocks enabled and gd valid - init serial console */
 611         preloader_console_init();
 612
 613         /* DDR initialization */
 614         vining2000_spl_dram_init();
 615
 616         /* Clear the BSS. */
 617         memset(__bss_start, 0, __bss_end - __bss_start);
 618
 619         /* load/boot image from boot device */
 620         board_init_r(NULL, 0);
 621 }
 622 #endif