1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 samtec automotive software & electronics gmbh
4 * Copyright (C) 2017-2019 softing automotive electronics gmbH
6 * Author: Christoph Fritz <chf.fritz@googlemail.com>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
16 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <linux/sizes.h>
21 #include <environment.h>
22 #include <fsl_esdhc.h>
27 #include <power/pmic.h>
28 #include <power/pfuze100_pmic.h>
30 #include <usb/ehci-ci.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
37 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
40 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \
41 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
44 #define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm
46 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \
47 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \
50 #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
51 PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
54 #define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
55 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
57 #define USDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
58 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
61 #define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
62 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)
64 #define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
69 gd->ram_size = imx_ddr_size();
74 static iomux_v3_cfg_t const uart1_pads[] = {
75 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
76 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
79 static iomux_v3_cfg_t const usdhc2_pads[] = {
80 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
81 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
82 MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
83 MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
84 MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85 MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 MX6_PAD_LCD1_VSYNC__GPIO3_IO_28 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
89 static iomux_v3_cfg_t const usdhc4_pads[] = {
90 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
91 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97 MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98 MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
99 MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100 MX6_PAD_SD4_RESET_B__USDHC4_RESET_B | MUX_PAD_CTRL(USDHC_RESET_CTRL),
103 static iomux_v3_cfg_t const fec1_pads[] = {
104 MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
105 MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
106 MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
107 MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
108 MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
109 MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
110 MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
111 MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
112 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) |
114 /* LAN8720 PHY Reset */
115 MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
118 static iomux_v3_cfg_t const pwm_led_pads[] = {
119 MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
120 MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
121 MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
124 static void setup_iomux_uart(void)
126 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
129 #define PHY_RESET IMX_GPIO_NR(5, 9)
131 int board_eth_init(bd_t *bis)
133 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
135 unsigned char eth1addr[6];
137 /* just to get secound mac address */
138 imx_get_mac_from_fuse(1, eth1addr);
139 if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
140 eth_env_set_enetaddr("eth1addr", eth1addr);
142 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
145 * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
146 * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
147 * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
149 clrsetbits_le32(&iomuxc_regs->gpr[1],
150 IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
151 IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
152 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
153 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
155 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
160 gpio_direction_output(PHY_RESET, 0);
162 gpio_set_value(PHY_RESET, 1);
165 ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
173 printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
174 gpio_set_value(PHY_RESET, 0);
178 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
180 static struct i2c_pads_info i2c_pad_info1 = {
182 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
183 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
184 .gp = IMX_GPIO_NR(1, 0),
187 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
188 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
189 .gp = IMX_GPIO_NR(1, 1),
193 static struct pmic *pfuze_init(unsigned char i2cbus)
199 ret = power_pfuze100_init(i2cbus);
203 p = pmic_get("PFUZE100");
208 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
209 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
211 /* Set SW1AB stanby volage to 0.975V */
212 pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
213 reg &= ~SW1x_STBY_MASK;
215 pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
217 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
218 pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
219 reg &= ~SW1xCONF_DVSSPEED_MASK;
220 reg |= SW1xCONF_DVSSPEED_4US;
221 pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
223 /* Set SW1C standby voltage to 0.975V */
224 pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
225 reg &= ~SW1x_STBY_MASK;
227 pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
229 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
230 pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
231 reg &= ~SW1xCONF_DVSSPEED_MASK;
232 reg |= SW1xCONF_DVSSPEED_4US;
233 pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
238 static int pfuze_mode_init(struct pmic *p, u32 mode)
240 unsigned char offset, i, switch_num;
244 pmic_reg_read(p, PFUZE100_DEVICEID, &id);
249 offset = PFUZE100_SW1CMODE;
250 } else if (id == 1) {
252 offset = PFUZE100_SW2MODE;
254 printf("Not supported, id=%d\n", id);
258 ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
260 printf("Set SW1AB mode error!\n");
264 for (i = 0; i < switch_num - 1; i++) {
265 ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
267 printf("Set switch 0x%x mode error!\n",
268 offset + i * SWITCH_SIZE);
276 int power_init_board(void)
281 p = pfuze_init(I2C_PMIC);
285 ret = pfuze_mode_init(p, APS_PFM);
292 #ifdef CONFIG_USB_EHCI_MX6
293 static iomux_v3_cfg_t const usb_otg_pads[] = {
295 MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
296 MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
298 MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
301 static void setup_iomux_usb(void)
303 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
304 ARRAY_SIZE(usb_otg_pads));
307 int board_usb_phy_mode(int port)
310 return USB_INIT_HOST;
312 return usb_phy_mode(port);
316 #ifdef CONFIG_PWM_IMX
317 static int set_pwm_leds(void)
321 imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
322 ARRAY_SIZE(pwm_led_pads));
323 /* enable backlight PWM 2, green LED */
324 ret = pwm_init(1, 0, 0);
327 /* duty cycle 200ns, period: 8000ns */
328 ret = pwm_config(1, 200, 8000);
335 /* enable backlight PWM 1, blue LED */
336 ret = pwm_init(0, 0, 0);
339 /* duty cycle 200ns, period: 8000ns */
340 ret = pwm_config(0, 200, 8000);
347 /* enable backlight PWM 6, red LED */
348 ret = pwm_init(5, 0, 0);
351 /* duty cycle 200ns, period: 8000ns */
352 ret = pwm_config(5, 200, 8000);
361 static int set_pwm_leds(void)
367 #define ADCx_HC0 0x00
369 #define ADCx_HS_C0 BIT(0)
371 #define ADCx_CFG 0x14
372 #define ADCx_CFG_SWMODE 0x308
374 #define ADCx_GC_CAL BIT(7)
376 static int read_adc(u32 *val)
379 void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
381 /* use software mode */
382 writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
384 /* start auto calibration */
385 setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
386 ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
390 /* start conversion */
391 writel(0, b + ADCx_HC0);
393 /* wait for conversion */
394 ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
399 *val = readl(b + ADCx_R0);
403 printf("ADC failure (ret=%i)\n", ret);
404 unmap_physmem(b, MAP_NOCACHE);
408 #define VAL_UPPER 2498
409 #define VAL_LOWER 1550
411 static int set_pin_state(void)
416 ret = read_adc(&val);
420 if (val >= VAL_UPPER)
421 env_set("pin_state", "connected");
422 else if (val < VAL_UPPER && val > VAL_LOWER)
423 env_set("pin_state", "open");
425 env_set("pin_state", "button");
430 int board_late_init(void)
434 ret = set_pwm_leds();
438 ret = set_pin_state();
443 int board_early_init_f(void)
452 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
453 {USDHC4_BASE_ADDR, 0, 8},
454 {USDHC2_BASE_ADDR, 0, 4},
457 #define USDHC2_CD_GPIO IMX_GPIO_NR(3, 28)
459 int board_mmc_getcd(struct mmc *mmc)
461 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
463 if (cfg->esdhc_base == USDHC4_BASE_ADDR)
465 if (cfg->esdhc_base == USDHC2_BASE_ADDR)
466 return !gpio_get_value(USDHC2_CD_GPIO);
471 int board_mmc_init(bd_t *bis)
476 * According to the board_mmc_init() the following map is done:
477 * (U-Boot device node) (Physical Port)
481 imx_iomux_v3_setup_multiple_pads(
482 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
483 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
485 imx_iomux_v3_setup_multiple_pads(
486 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
487 gpio_direction_input(USDHC2_CD_GPIO);
488 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
490 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
492 printf("Warning: failed to initialize USDHC4\n");
496 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
498 printf("Warning: failed to initialize USDHC2\n");
507 /* Address of boot parameters */
508 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
510 #ifdef CONFIG_SYS_I2C_MXC
511 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
519 puts("Board: VIN|ING 2000\n");