board/softing/vining_2000/vining_2000.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 samtec automotive software & electronics gmbh
   4  * Copyright (C) 2017-2019 softing automotive electronics gmbH
   5  *
   6  * Author: Christoph Fritz <chf.fritz@googlemail.com>
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/gpio.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/io.h>
  18 #include <asm/mach-imx/mxc_i2c.h>
  19 #include <linux/sizes.h>
  20 #include <common.h>
  21 #include <environment.h>
  22 #include <fsl_esdhc.h>
  23 #include <mmc.h>
  24 #include <i2c.h>
  25 #include <miiphy.h>
  26 #include <netdev.h>
  27 #include <power/pmic.h>
  28 #include <power/pfuze100_pmic.h>
  29 #include <usb.h>
  30 #include <usb/ehci-ci.h>
  31 #include <pwm.h>
  32 #include <wait_bit.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #define UART_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |     \
  37         PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |   \
  38         PAD_CTL_SRE_FAST)
  39
  40 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE |     \
  41         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm |                \
  42         PAD_CTL_SRE_FAST)
  43
  44 #define ENET_CLK_PAD_CTRL  PAD_CTL_DSE_34ohm
  45
  46 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE |                        \
  47         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH |            \
  48         PAD_CTL_SRE_FAST)
  49
  50 #define I2C_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |      \
  51         PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED |         \
  52         PAD_CTL_DSE_40ohm)
  53
  54 #define USDHC_CLK_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_SPEED_MED |  \
  55         PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
  56
  57 #define USDHC_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP |     \
  58         PAD_CTL_PKE |  PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm |  \
  59         PAD_CTL_SRE_FAST)
  60
  61 #define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP |    \
  62         PAD_CTL_PKE |  PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)
  63
  64 #define GPIO_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |     \
  65         PAD_CTL_PKE)
  66
  67 int dram_init(void)
  68 {
  69         gd->ram_size = imx_ddr_size();
  70
  71         return 0;
  72 }
  73
  74 static iomux_v3_cfg_t const uart1_pads[] = {
  75         MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  76         MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  77 };
  78
  79 static iomux_v3_cfg_t const fec1_pads[] = {
  80         MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  81         MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82         MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  83         MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  84         MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85         MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86         MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  87         MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) |
  89                 MUX_MODE_SION,
  90         /* LAN8720 PHY Reset */
  91         MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
  92 };
  93
  94 static iomux_v3_cfg_t const pwm_led_pads[] = {
  95         MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
  96         MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
  97         MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
  98 };
  99
 100 static void setup_iomux_uart(void)
 101 {
 102         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 103 }
 104
 105 #define PHY_RESET IMX_GPIO_NR(5, 9)
 106
 107 int board_eth_init(bd_t *bis)
 108 {
 109         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 110         int ret;
 111         unsigned char eth1addr[6];
 112
 113         /* just to get secound mac address */
 114         imx_get_mac_from_fuse(1, eth1addr);
 115         if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
 116                 eth_env_set_enetaddr("eth1addr", eth1addr);
 117
 118         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 119
 120         /*
 121          * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
 122          * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
 123          * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
 124          */
 125         clrsetbits_le32(&iomuxc_regs->gpr[1],
 126                         IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
 127                         IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
 128                         IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
 129                         IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
 130
 131         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 132         if (ret)
 133                 goto eth_fail;
 134
 135         /* reset phy */
 136         gpio_request(PHY_RESET, "PHY-reset");
 137         gpio_direction_output(PHY_RESET, 0);
 138         mdelay(16);
 139         gpio_set_value(PHY_RESET, 1);
 140         mdelay(1);
 141
 142         ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
 143                                         IMX_FEC_BASE);
 144         if (ret)
 145                 goto eth_fail;
 146
 147         return ret;
 148
 149 eth_fail:
 150         printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
 151         gpio_set_value(PHY_RESET, 0);
 152         return ret;
 153 }
 154
 155 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 156 /* I2C1 for PMIC */
 157 static struct i2c_pads_info i2c_pad_info1 = {
 158         .scl = {
 159                 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
 160                 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
 161                 .gp = IMX_GPIO_NR(1, 0),
 162         },
 163         .sda = {
 164                 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
 165                 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
 166                 .gp = IMX_GPIO_NR(1, 1),
 167         },
 168 };
 169
 170 static struct pmic *pfuze_init(unsigned char i2cbus)
 171 {
 172         struct pmic *p;
 173         int ret;
 174         u32 reg;
 175
 176         ret = power_pfuze100_init(i2cbus);
 177         if (ret)
 178                 return NULL;
 179
 180         p = pmic_get("PFUZE100");
 181         ret = pmic_probe(p);
 182         if (ret)
 183                 return NULL;
 184
 185         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 186         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 187
 188         /* Set SW1AB stanby volage to 0.975V */
 189         pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 190         reg &= ~SW1x_STBY_MASK;
 191         reg |= SW1x_0_975V;
 192         pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
 193
 194         /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 195         pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
 196         reg &= ~SW1xCONF_DVSSPEED_MASK;
 197         reg |= SW1xCONF_DVSSPEED_4US;
 198         pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
 199
 200         /* Set SW1C standby voltage to 0.975V */
 201         pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
 202         reg &= ~SW1x_STBY_MASK;
 203         reg |= SW1x_0_975V;
 204         pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
 205
 206         /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
 207         pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
 208         reg &= ~SW1xCONF_DVSSPEED_MASK;
 209         reg |= SW1xCONF_DVSSPEED_4US;
 210         pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
 211
 212         return p;
 213 }
 214
 215 static int pfuze_mode_init(struct pmic *p, u32 mode)
 216 {
 217         unsigned char offset, i, switch_num;
 218         u32 id;
 219         int ret;
 220
 221         pmic_reg_read(p, PFUZE100_DEVICEID, &id);
 222         id = id & 0xf;
 223
 224         if (id == 0) {
 225                 switch_num = 6;
 226                 offset = PFUZE100_SW1CMODE;
 227         } else if (id == 1) {
 228                 switch_num = 4;
 229                 offset = PFUZE100_SW2MODE;
 230         } else {
 231                 printf("Not supported, id=%d\n", id);
 232                 return -EINVAL;
 233         }
 234
 235         ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
 236         if (ret < 0) {
 237                 printf("Set SW1AB mode error!\n");
 238                 return ret;
 239         }
 240
 241         for (i = 0; i < switch_num - 1; i++) {
 242                 ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
 243                 if (ret < 0) {
 244                         printf("Set switch 0x%x mode error!\n",
 245                                offset + i * SWITCH_SIZE);
 246                         return ret;
 247                 }
 248         }
 249
 250         return ret;
 251 }
 252
 253 int power_init_board(void)
 254 {
 255         struct pmic *p;
 256         int ret;
 257
 258         p = pfuze_init(I2C_PMIC);
 259         if (!p)
 260                 return -ENODEV;
 261
 262         ret = pfuze_mode_init(p, APS_PFM);
 263         if (ret < 0)
 264                 return ret;
 265
 266         return 0;
 267 }
 268
 269 #ifdef CONFIG_USB_EHCI_MX6
 270 static iomux_v3_cfg_t const usb_otg_pads[] = {
 271         /* OGT1 */
 272         MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 273         MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
 274         /* OTG2 */
 275         MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
 276 };
 277
 278 static void setup_iomux_usb(void)
 279 {
 280         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 281                                          ARRAY_SIZE(usb_otg_pads));
 282 }
 283
 284 int board_usb_phy_mode(int port)
 285 {
 286         if (port == 1)
 287                 return USB_INIT_HOST;
 288         else
 289                 return usb_phy_mode(port);
 290 }
 291 #endif
 292
 293 #ifdef CONFIG_PWM_IMX
 294 static int set_pwm_leds(void)
 295 {
 296         int ret;
 297
 298         imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
 299                                          ARRAY_SIZE(pwm_led_pads));
 300         /* enable backlight PWM 2, green LED */
 301         ret = pwm_init(1, 0, 0);
 302         if (ret)
 303                 goto error;
 304         /* duty cycle 200ns, period: 8000ns */
 305         ret = pwm_config(1, 200, 8000);
 306         if (ret)
 307                 goto error;
 308         ret = pwm_enable(1);
 309         if (ret)
 310                 goto error;
 311
 312         /* enable backlight PWM 1, blue LED */
 313         ret = pwm_init(0, 0, 0);
 314         if (ret)
 315                 goto error;
 316         /* duty cycle 200ns, period: 8000ns */
 317         ret = pwm_config(0, 200, 8000);
 318         if (ret)
 319                 goto error;
 320         ret = pwm_enable(0);
 321         if (ret)
 322                 goto error;
 323
 324         /* enable backlight PWM 6, red LED */
 325         ret = pwm_init(5, 0, 0);
 326         if (ret)
 327                 goto error;
 328         /* duty cycle 200ns, period: 8000ns */
 329         ret = pwm_config(5, 200, 8000);
 330         if (ret)
 331                 goto error;
 332         ret = pwm_enable(5);
 333
 334 error:
 335         return ret;
 336 }
 337 #else
 338 static int set_pwm_leds(void)
 339 {
 340         return 0;
 341 }
 342 #endif
 343
 344 #define ADCx_HC0        0x00
 345 #define ADCx_HS         0x08
 346 #define ADCx_HS_C0      BIT(0)
 347 #define ADCx_R0         0x0c
 348 #define ADCx_CFG        0x14
 349 #define ADCx_CFG_SWMODE 0x308
 350 #define ADCx_GC         0x18
 351 #define ADCx_GC_CAL     BIT(7)
 352
 353 static int read_adc(u32 *val)
 354 {
 355         int ret;
 356         void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
 357
 358         /* use software mode */
 359         writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
 360
 361         /* start auto calibration */
 362         setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
 363         ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
 364         if (ret)
 365                 goto adc_exit;
 366
 367         /* start conversion */
 368         writel(0, b + ADCx_HC0);
 369
 370         /* wait for conversion */
 371         ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
 372         if (ret)
 373                 goto adc_exit;
 374
 375         /* read result */
 376         *val = readl(b + ADCx_R0);
 377
 378 adc_exit:
 379         if (ret)
 380                 printf("ADC failure (ret=%i)\n", ret);
 381         unmap_physmem(b, MAP_NOCACHE);
 382         return ret;
 383 }
 384
 385 #define VAL_UPPER       2498
 386 #define VAL_LOWER       1550
 387
 388 static int set_pin_state(void)
 389 {
 390         u32 val;
 391         int ret;
 392
 393         ret = read_adc(&val);
 394         if (ret)
 395                 return ret;
 396
 397         if (val >= VAL_UPPER)
 398                 env_set("pin_state", "connected");
 399         else if (val < VAL_UPPER && val > VAL_LOWER)
 400                 env_set("pin_state", "open");
 401         else
 402                 env_set("pin_state", "button");
 403
 404         return ret;
 405 }
 406
 407 int board_late_init(void)
 408 {
 409         int ret;
 410
 411         ret = set_pwm_leds();
 412         if (ret)
 413                 return ret;
 414
 415         ret = set_pin_state();
 416
 417         return ret;
 418 }
 419
 420 int board_early_init_f(void)
 421 {
 422         setup_iomux_uart();
 423
 424         setup_iomux_usb();
 425
 426         return 0;
 427 }
 428
 429 int board_init(void)
 430 {
 431         /* Address of boot parameters */
 432         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 433
 434 #ifdef CONFIG_SYS_I2C_MXC
 435         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 436 #endif
 437
 438         return 0;
 439 }
 440
 441 int checkboard(void)
 442 {
 443         puts("Board: VIN|ING 2000\n");
 444
 445         return 0;
 446 }