1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 samtec automotive software & electronics gmbh
4 * Copyright (C) 2017-2019 softing automotive electronics gmbH
6 * Author: Christoph Fritz <chf.fritz@googlemail.com>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <asm/arch/sys_proto.h>
18 #include <asm/mach-imx/iomux-v3.h>
20 #include <asm/mach-imx/mxc_i2c.h>
22 #include <linux/sizes.h>
24 #include <fsl_esdhc_imx.h>
29 #include <power/pmic.h>
30 #include <power/pfuze100_pmic.h>
32 #include <usb/ehci-ci.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
39 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
42 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \
43 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
46 #define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm
48 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \
49 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \
52 #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
53 PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
56 #define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
57 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
59 #define USDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
60 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
63 #define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
64 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)
66 #define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
71 gd->ram_size = imx_ddr_size();
76 static iomux_v3_cfg_t const pwm_led_pads[] = {
77 MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
78 MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
79 MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
82 static int board_net_init(void)
84 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
85 unsigned char eth1addr[6];
88 /* just to get second mac address */
89 imx_get_mac_from_fuse(1, eth1addr);
90 if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
91 eth_env_set_enetaddr("eth1addr", eth1addr);
94 * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
95 * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
96 * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
98 clrsetbits_le32(&iomuxc_regs->gpr[1],
99 IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
100 IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
101 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
102 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
104 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
108 ret = enable_fec_anatop_clock(1, ENET_50MHZ);
115 printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
119 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
121 static struct i2c_pads_info i2c_pad_info1 = {
123 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
124 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
125 .gp = IMX_GPIO_NR(1, 0),
128 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
129 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
130 .gp = IMX_GPIO_NR(1, 1),
134 static struct pmic *pfuze_init(unsigned char i2cbus)
140 ret = power_pfuze100_init(i2cbus);
144 p = pmic_get("PFUZE100");
149 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
150 printf("PMIC: PFUZE%i00 ID=0x%02x\n", (reg & 1) ? 2 : 1, reg);
152 /* Set SW1AB stanby volage to 0.975V */
153 pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
154 reg &= ~SW1x_STBY_MASK;
156 pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
158 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
159 pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
160 reg &= ~SW1xCONF_DVSSPEED_MASK;
161 reg |= SW1xCONF_DVSSPEED_4US;
162 pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
164 /* Set SW1C standby voltage to 0.975V */
165 pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
166 reg &= ~SW1x_STBY_MASK;
168 pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
170 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
171 pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
172 reg &= ~SW1xCONF_DVSSPEED_MASK;
173 reg |= SW1xCONF_DVSSPEED_4US;
174 pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
179 static int pfuze_mode_init(struct pmic *p, u32 mode)
181 unsigned char offset, i, switch_num;
185 pmic_reg_read(p, PFUZE100_DEVICEID, &id);
190 offset = PFUZE100_SW1CMODE;
191 } else if (id == 1) {
193 offset = PFUZE100_SW2MODE;
195 printf("Not supported, id=%d\n", id);
199 ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
201 printf("Set SW1AB mode error!\n");
205 for (i = 0; i < switch_num - 1; i++) {
206 ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
208 printf("Set switch 0x%x mode error!\n",
209 offset + i * SWITCH_SIZE);
217 int power_init_board(void)
222 p = pfuze_init(I2C_PMIC);
226 ret = pfuze_mode_init(p, APS_PFM);
230 set_ldo_voltage(LDO_ARM, 1175); /* Set VDDARM to 1.175V */
231 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
236 #ifdef CONFIG_USB_EHCI_MX6
237 static iomux_v3_cfg_t const usb_otg_pads[] = {
239 MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
240 MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
242 MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
245 static void setup_iomux_usb(void)
247 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
248 ARRAY_SIZE(usb_otg_pads));
251 int board_usb_phy_mode(int port)
254 return USB_INIT_HOST;
256 return usb_phy_mode(port);
260 #ifdef CONFIG_PWM_IMX
261 static int set_pwm_leds(void)
265 imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
266 ARRAY_SIZE(pwm_led_pads));
267 /* enable backlight PWM 2, green LED */
268 ret = pwm_init(1, 0, 0);
271 /* duty cycle 200ns, period: 8000ns */
272 ret = pwm_config(1, 200, 8000);
279 /* enable backlight PWM 1, blue LED */
280 ret = pwm_init(0, 0, 0);
283 /* duty cycle 200ns, period: 8000ns */
284 ret = pwm_config(0, 200, 8000);
291 /* enable backlight PWM 6, red LED */
292 ret = pwm_init(5, 0, 0);
295 /* duty cycle 200ns, period: 8000ns */
296 ret = pwm_config(5, 200, 8000);
305 static int set_pwm_leds(void)
311 #define ADCx_HC0 0x00
313 #define ADCx_HS_C0 BIT(0)
315 #define ADCx_CFG 0x14
316 #define ADCx_CFG_SWMODE 0x308
318 #define ADCx_GC_CAL BIT(7)
320 static int read_adc(u32 *val)
323 void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
325 /* use software mode */
326 writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
328 /* start auto calibration */
329 setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
330 ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
334 /* start conversion */
335 writel(0, b + ADCx_HC0);
337 /* wait for conversion */
338 ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
343 *val = readl(b + ADCx_R0);
347 printf("ADC failure (ret=%i)\n", ret);
348 unmap_physmem(b, MAP_NOCACHE);
352 #define VAL_UPPER 2498
353 #define VAL_LOWER 1550
355 static int set_pin_state(void)
360 ret = read_adc(&val);
364 if (val >= VAL_UPPER)
365 env_set("pin_state", "connected");
366 else if (val < VAL_UPPER && val > VAL_LOWER)
367 env_set("pin_state", "open");
369 env_set("pin_state", "button");
374 int board_late_init(void)
378 ret = set_pwm_leds();
382 ret = set_pin_state();
387 int board_early_init_f(void)
396 /* Address of boot parameters */
397 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
399 #ifdef CONFIG_SYS_I2C_MXC
400 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
403 return board_net_init();
408 puts("Board: VIN|ING 2000\n");
413 #define PCIE_PHY_PUP_REQ BIT(7)
415 void board_preboot_os(void)
417 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
418 struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
420 /* Bring the PCI power domain up, so that old vendorkernel works. */
421 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
422 setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
423 setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
426 #ifdef CONFIG_SPL_BUILD
427 #include <linux/libfdt.h>
429 #include <asm/arch/mx6-ddr.h>
431 static iomux_v3_cfg_t const pcie_pads[] = {
432 MX6_PAD_NAND_DATA02__GPIO4_IO_6 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
435 static iomux_v3_cfg_t const uart_pads[] = {
436 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
437 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
440 static iomux_v3_cfg_t const usdhc4_pads[] = {
441 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
442 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
443 MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
444 MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
445 MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
446 MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
447 MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
448 MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
449 MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
450 MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
453 static void vining2000_spl_setup_iomux_pcie(void)
455 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
458 static void vining2000_spl_setup_iomux_uart(void)
460 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
463 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
465 int board_mmc_init(bd_t *bis)
467 imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
469 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
470 gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
471 return fsl_esdhc_initialize(bis, &usdhc_cfg);
474 int board_mmc_getcd(struct mmc *mmc)
479 const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
480 .dram_dqm0 = 0x00000028,
481 .dram_dqm1 = 0x00000028,
482 .dram_dqm2 = 0x00000028,
483 .dram_dqm3 = 0x00000028,
484 .dram_ras = 0x00000028,
485 .dram_cas = 0x00000028,
486 .dram_odt0 = 0x00000028,
487 .dram_odt1 = 0x00000028,
488 .dram_sdba2 = 0x00000000,
489 .dram_sdcke0 = 0x00003000,
490 .dram_sdcke1 = 0x00003000,
491 .dram_sdclk_0 = 0x00000030,
492 .dram_sdqs0 = 0x00000028,
493 .dram_sdqs1 = 0x00000028,
494 .dram_sdqs2 = 0x00000028,
495 .dram_sdqs3 = 0x00000028,
496 .dram_reset = 0x00000028,
499 const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
500 .grp_addds = 0x00000028,
501 .grp_b0ds = 0x00000028,
502 .grp_b1ds = 0x00000028,
503 .grp_b2ds = 0x00000028,
504 .grp_b3ds = 0x00000028,
505 .grp_ctlds = 0x00000028,
506 .grp_ddr_type = 0x000c0000,
507 .grp_ddrmode = 0x00020000,
508 .grp_ddrmode_ctl = 0x00020000,
509 .grp_ddrpke = 0x00000000,
512 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
513 .p0_mpwldectrl0 = 0x0022001C,
514 .p0_mpwldectrl1 = 0x001F001A,
515 .p0_mpdgctrl0 = 0x01380134,
516 .p0_mpdgctrl1 = 0x0124011C,
517 .p0_mprddlctl = 0x42404444,
518 .p0_mpwrdlctl = 0x36383C38,
521 static struct mx6_ddr3_cfg mem_ddr = {
534 static void ccgr_init(void)
536 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
538 writel(0xF000000F, &ccm->CCGR0); /* AIPS_TZ{1,2,3} */
539 writel(0x303C0000, &ccm->CCGR1); /* GPT, OCRAM */
540 writel(0x00FFFCC0, &ccm->CCGR2); /* IPMUX, I2C1, I2C3 */
541 writel(0x3F300030, &ccm->CCGR3); /* OCRAM, MMDC, ENET */
542 writel(0x0000C003, &ccm->CCGR4); /* PCI, PL301 */
543 writel(0x0F0330C3, &ccm->CCGR5); /* UART, ROM */
544 writel(0x00000F00, &ccm->CCGR6); /* SDHI4, EIM */
547 static void vining2000_spl_dram_init(void)
549 struct mx6_ddr_sysinfo sysinfo = {
550 .dsize = mem_ddr.width / 32,
554 .rtt_wr = 1, /* RTT_wr = RZQ/4 */
555 .rtt_nom = 1, /* RTT_Nom = RZQ/4 */
556 .walat = 1, /* Write additional latency */
557 .ralat = 5, /* Read additional latency */
558 .mif3_mode = 3, /* Command prediction working mode */
559 .bi_on = 1, /* Bank interleaving enabled */
560 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
561 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
562 .ddr_type = DDR_TYPE_DDR3,
563 .refsel = 1, /* Refresh cycles at 32KHz */
564 .refr = 7, /* 8 refresh commands per refresh cycle */
567 mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
568 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
570 /* Perform DDR DRAM calibration */
572 mmdc_do_write_level_calibration(&sysinfo);
573 mmdc_do_dqs_calibration(&sysinfo);
576 void board_init_f(ulong dummy)
578 /* setup AIPS and disable watchdog */
584 vining2000_spl_setup_iomux_pcie();
585 vining2000_spl_setup_iomux_uart();
590 /* reset the PCIe device */
591 gpio_set_value(IMX_GPIO_NR(4, 6), 1);
593 gpio_set_value(IMX_GPIO_NR(4, 6), 0);
595 /* UART clocks enabled and gd valid - init serial console */
596 preloader_console_init();
598 /* DDR initialization */
599 vining2000_spl_dram_init();
602 memset(__bss_start, 0, __bss_end - __bss_start);
604 /* load/boot image from boot device */
605 board_init_r(NULL, 0);