board/softing/vining_2000/vining_2000.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 samtec automotive software & electronics gmbh
   4  * Copyright (C) 2017-2019 softing automotive electronics gmbH
   5  *
   6  * Author: Christoph Fritz <chf.fritz@googlemail.com>
   7  */
   8
   9 #include <init.h>
  10 #include <net.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/gpio.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/io.h>
  20 #include <asm/mach-imx/mxc_i2c.h>
  21 #include <env.h>
  22 #include <linux/bitops.h>
  23 #include <linux/delay.h>
  24 #include <linux/sizes.h>
  25 #include <common.h>
  26 #include <fsl_esdhc_imx.h>
  27 #include <mmc.h>
  28 #include <i2c.h>
  29 #include <miiphy.h>
  30 #include <netdev.h>
  31 #include <power/pmic.h>
  32 #include <power/pfuze100_pmic.h>
  33 #include <usb.h>
  34 #include <usb/ehci-ci.h>
  35 #include <pwm.h>
  36 #include <wait_bit.h>
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #define UART_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |     \
  41         PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |   \
  42         PAD_CTL_SRE_FAST)
  43
  44 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE |     \
  45         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm |                \
  46         PAD_CTL_SRE_FAST)
  47
  48 #define ENET_CLK_PAD_CTRL  PAD_CTL_DSE_34ohm
  49
  50 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE |                        \
  51         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH |            \
  52         PAD_CTL_SRE_FAST)
  53
  54 #define I2C_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |      \
  55         PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED |         \
  56         PAD_CTL_DSE_40ohm)
  57
  58 #define USDHC_CLK_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_SPEED_MED |  \
  59         PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
  60
  61 #define USDHC_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP |     \
  62         PAD_CTL_PKE |  PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm |  \
  63         PAD_CTL_SRE_FAST)
  64
  65 #define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP |    \
  66         PAD_CTL_PKE |  PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)
  67
  68 #define GPIO_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |     \
  69         PAD_CTL_PKE)
  70
  71 int dram_init(void)
  72 {
  73         gd->ram_size = imx_ddr_size();
  74
  75         return 0;
  76 }
  77
  78 static iomux_v3_cfg_t const pwm_led_pads[] = {
  79         MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
  80         MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
  81         MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
  82 };
  83
  84 static int board_net_init(void)
  85 {
  86         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  87         unsigned char eth1addr[6];
  88         int ret;
  89
  90         /* just to get second mac address */
  91         imx_get_mac_from_fuse(1, eth1addr);
  92         if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
  93                 eth_env_set_enetaddr("eth1addr", eth1addr);
  94
  95         /*
  96          * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
  97          * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
  98          * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
  99          */
 100         clrsetbits_le32(&iomuxc_regs->gpr[1],
 101                         IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
 102                         IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
 103                         IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
 104                         IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
 105
 106         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 107         if (ret)
 108                 goto eth_fail;
 109
 110         ret = enable_fec_anatop_clock(1, ENET_50MHZ);
 111         if (ret)
 112                 goto eth_fail;
 113
 114         return ret;
 115
 116 eth_fail:
 117         printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
 118         return ret;
 119 }
 120
 121 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 122 /* I2C1 for PMIC */
 123 static struct i2c_pads_info i2c_pad_info1 = {
 124         .scl = {
 125                 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
 126                 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
 127                 .gp = IMX_GPIO_NR(1, 0),
 128         },
 129         .sda = {
 130                 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
 131                 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
 132                 .gp = IMX_GPIO_NR(1, 1),
 133         },
 134 };
 135
 136 static struct pmic *pfuze_init(unsigned char i2cbus)
 137 {
 138         struct pmic *p;
 139         int ret;
 140         u32 reg;
 141
 142         ret = power_pfuze100_init(i2cbus);
 143         if (ret)
 144                 return NULL;
 145
 146         p = pmic_get("PFUZE100");
 147         ret = pmic_probe(p);
 148         if (ret)
 149                 return NULL;
 150
 151         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 152         printf("PMIC:  PFUZE%i00 ID=0x%02x\n", (reg & 1) ? 2 : 1, reg);
 153
 154         /* Set SW1AB stanby volage to 0.975V */
 155         pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 156         reg &= ~SW1x_STBY_MASK;
 157         reg |= SW1x_0_975V;
 158         pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
 159
 160         /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 161         pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
 162         reg &= ~SW1xCONF_DVSSPEED_MASK;
 163         reg |= SW1xCONF_DVSSPEED_4US;
 164         pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
 165
 166         /* Set SW1C standby voltage to 0.975V */
 167         pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
 168         reg &= ~SW1x_STBY_MASK;
 169         reg |= SW1x_0_975V;
 170         pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
 171
 172         /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
 173         pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
 174         reg &= ~SW1xCONF_DVSSPEED_MASK;
 175         reg |= SW1xCONF_DVSSPEED_4US;
 176         pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
 177
 178         return p;
 179 }
 180
 181 static int pfuze_mode_init(struct pmic *p, u32 mode)
 182 {
 183         unsigned char offset, i, switch_num;
 184         u32 id;
 185         int ret;
 186
 187         pmic_reg_read(p, PFUZE100_DEVICEID, &id);
 188         id = id & 0xf;
 189
 190         if (id == 0) {
 191                 switch_num = 6;
 192                 offset = PFUZE100_SW1CMODE;
 193         } else if (id == 1) {
 194                 switch_num = 4;
 195                 offset = PFUZE100_SW2MODE;
 196         } else {
 197                 printf("Not supported, id=%d\n", id);
 198                 return -EINVAL;
 199         }
 200
 201         ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
 202         if (ret < 0) {
 203                 printf("Set SW1AB mode error!\n");
 204                 return ret;
 205         }
 206
 207         for (i = 0; i < switch_num - 1; i++) {
 208                 ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
 209                 if (ret < 0) {
 210                         printf("Set switch 0x%x mode error!\n",
 211                                offset + i * SWITCH_SIZE);
 212                         return ret;
 213                 }
 214         }
 215
 216         return ret;
 217 }
 218
 219 int power_init_board(void)
 220 {
 221         struct pmic *p;
 222         int ret;
 223
 224         p = pfuze_init(I2C_PMIC);
 225         if (!p)
 226                 return -ENODEV;
 227
 228         ret = pfuze_mode_init(p, APS_PFM);
 229         if (ret < 0)
 230                 return ret;
 231
 232         set_ldo_voltage(LDO_ARM, 1175); /* Set VDDARM to 1.175V */
 233         set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
 234
 235         return 0;
 236 }
 237
 238 #ifdef CONFIG_USB_EHCI_MX6
 239 static iomux_v3_cfg_t const usb_otg_pads[] = {
 240         /* OGT1 */
 241         MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 242         MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
 243         /* OTG2 */
 244         MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
 245 };
 246
 247 static void setup_iomux_usb(void)
 248 {
 249         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 250                                          ARRAY_SIZE(usb_otg_pads));
 251 }
 252
 253 int board_usb_phy_mode(int port)
 254 {
 255         if (port == 1)
 256                 return USB_INIT_HOST;
 257         else
 258                 return usb_phy_mode(port);
 259 }
 260 #endif
 261
 262 #ifdef CONFIG_PWM_IMX
 263 static int set_pwm_leds(void)
 264 {
 265         int ret;
 266
 267         imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
 268                                          ARRAY_SIZE(pwm_led_pads));
 269         /* enable backlight PWM 2, green LED */
 270         ret = pwm_init(1, 0, 0);
 271         if (ret)
 272                 goto error;
 273         /* duty cycle 200ns, period: 8000ns */
 274         ret = pwm_config(1, 200, 8000);
 275         if (ret)
 276                 goto error;
 277         ret = pwm_enable(1);
 278         if (ret)
 279                 goto error;
 280
 281         /* enable backlight PWM 1, blue LED */
 282         ret = pwm_init(0, 0, 0);
 283         if (ret)
 284                 goto error;
 285         /* duty cycle 200ns, period: 8000ns */
 286         ret = pwm_config(0, 200, 8000);
 287         if (ret)
 288                 goto error;
 289         ret = pwm_enable(0);
 290         if (ret)
 291                 goto error;
 292
 293         /* enable backlight PWM 6, red LED */
 294         ret = pwm_init(5, 0, 0);
 295         if (ret)
 296                 goto error;
 297         /* duty cycle 200ns, period: 8000ns */
 298         ret = pwm_config(5, 200, 8000);
 299         if (ret)
 300                 goto error;
 301         ret = pwm_enable(5);
 302
 303 error:
 304         return ret;
 305 }
 306 #else
 307 static int set_pwm_leds(void)
 308 {
 309         return 0;
 310 }
 311 #endif
 312
 313 #define ADCx_HC0        0x00
 314 #define ADCx_HS         0x08
 315 #define ADCx_HS_C0      BIT(0)
 316 #define ADCx_R0         0x0c
 317 #define ADCx_CFG        0x14
 318 #define ADCx_CFG_SWMODE 0x308
 319 #define ADCx_GC         0x18
 320 #define ADCx_GC_CAL     BIT(7)
 321
 322 static int read_adc(u32 *val)
 323 {
 324         int ret;
 325         void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
 326
 327         /* use software mode */
 328         writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
 329
 330         /* start auto calibration */
 331         setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
 332         ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
 333         if (ret)
 334                 goto adc_exit;
 335
 336         /* start conversion */
 337         writel(0, b + ADCx_HC0);
 338
 339         /* wait for conversion */
 340         ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
 341         if (ret)
 342                 goto adc_exit;
 343
 344         /* read result */
 345         *val = readl(b + ADCx_R0);
 346
 347 adc_exit:
 348         if (ret)
 349                 printf("ADC failure (ret=%i)\n", ret);
 350         unmap_physmem(b, MAP_NOCACHE);
 351         return ret;
 352 }
 353
 354 #define VAL_UPPER       2498
 355 #define VAL_LOWER       1550
 356
 357 static int set_pin_state(void)
 358 {
 359         u32 val;
 360         int ret;
 361
 362         ret = read_adc(&val);
 363         if (ret)
 364                 return ret;
 365
 366         if (val >= VAL_UPPER)
 367                 env_set("pin_state", "connected");
 368         else if (val < VAL_UPPER && val > VAL_LOWER)
 369                 env_set("pin_state", "open");
 370         else
 371                 env_set("pin_state", "button");
 372
 373         return ret;
 374 }
 375
 376 int board_late_init(void)
 377 {
 378         int ret;
 379
 380         ret = set_pwm_leds();
 381         if (ret)
 382                 return ret;
 383
 384         ret = set_pin_state();
 385
 386         return ret;
 387 }
 388
 389 int board_early_init_f(void)
 390 {
 391         setup_iomux_usb();
 392
 393         return 0;
 394 }
 395
 396 int board_init(void)
 397 {
 398         /* Address of boot parameters */
 399         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 400
 401 #ifdef CONFIG_SYS_I2C_MXC
 402         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 403 #endif
 404
 405         return board_net_init();
 406 }
 407
 408 int checkboard(void)
 409 {
 410         puts("Board: VIN|ING 2000\n");
 411
 412         return 0;
 413 }
 414
 415 #define PCIE_PHY_PUP_REQ                BIT(7)
 416
 417 void board_preboot_os(void)
 418 {
 419         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 420         struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
 421
 422         /* Bring the PCI power domain up, so that old vendorkernel works. */
 423         setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
 424         setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
 425         setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
 426 }
 427
 428 #ifdef CONFIG_SPL_BUILD
 429 #include <linux/libfdt.h>
 430 #include <spl.h>
 431 #include <asm/arch/mx6-ddr.h>
 432
 433 static iomux_v3_cfg_t const pcie_pads[] = {
 434         MX6_PAD_NAND_DATA02__GPIO4_IO_6 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
 435 };
 436
 437 static iomux_v3_cfg_t const uart_pads[] = {
 438         MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 439         MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 440 };
 441
 442 static iomux_v3_cfg_t const usdhc4_pads[] = {
 443         MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 444         MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 445         MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 446         MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 447         MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 448         MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 449         MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 450         MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 451         MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 452         MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 453 };
 454
 455 static void vining2000_spl_setup_iomux_pcie(void)
 456 {
 457         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 458 }
 459
 460 static void vining2000_spl_setup_iomux_uart(void)
 461 {
 462         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 463 }
 464
 465 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
 466
 467 int board_mmc_init(bd_t *bis)
 468 {
 469         imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 470
 471         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 472         gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
 473         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 474 }
 475
 476 int board_mmc_getcd(struct mmc *mmc)
 477 {
 478         return 1;
 479 }
 480
 481 const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
 482         .dram_dqm0              = 0x00000028,
 483         .dram_dqm1              = 0x00000028,
 484         .dram_dqm2              = 0x00000028,
 485         .dram_dqm3              = 0x00000028,
 486         .dram_ras               = 0x00000028,
 487         .dram_cas               = 0x00000028,
 488         .dram_odt0              = 0x00000028,
 489         .dram_odt1              = 0x00000028,
 490         .dram_sdba2             = 0x00000000,
 491         .dram_sdcke0            = 0x00003000,
 492         .dram_sdcke1            = 0x00003000,
 493         .dram_sdclk_0           = 0x00000030,
 494         .dram_sdqs0             = 0x00000028,
 495         .dram_sdqs1             = 0x00000028,
 496         .dram_sdqs2             = 0x00000028,
 497         .dram_sdqs3             = 0x00000028,
 498         .dram_reset             = 0x00000028,
 499 };
 500
 501 const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
 502         .grp_addds              = 0x00000028,
 503         .grp_b0ds               = 0x00000028,
 504         .grp_b1ds               = 0x00000028,
 505         .grp_b2ds               = 0x00000028,
 506         .grp_b3ds               = 0x00000028,
 507         .grp_ctlds              = 0x00000028,
 508         .grp_ddr_type           = 0x000c0000,
 509         .grp_ddrmode            = 0x00020000,
 510         .grp_ddrmode_ctl        = 0x00020000,
 511         .grp_ddrpke             = 0x00000000,
 512 };
 513
 514 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
 515         .p0_mpwldectrl0         = 0x0022001C,
 516         .p0_mpwldectrl1         = 0x001F001A,
 517         .p0_mpdgctrl0           = 0x01380134,
 518         .p0_mpdgctrl1           = 0x0124011C,
 519         .p0_mprddlctl           = 0x42404444,
 520         .p0_mpwrdlctl           = 0x36383C38,
 521 };
 522
 523 static struct mx6_ddr3_cfg mem_ddr = {
 524         .mem_speed      = 1600,
 525         .density        = 4,
 526         .width          = 32,
 527         .banks          = 8,
 528         .rowaddr        = 15,
 529         .coladdr        = 10,
 530         .pagesz         = 2,
 531         .trcd           = 1391,
 532         .trcmin         = 4875,
 533         .trasmin        = 3500,
 534 };
 535
 536 static void ccgr_init(void)
 537 {
 538         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 539
 540         writel(0xF000000F, &ccm->CCGR0);        /* AIPS_TZ{1,2,3} */
 541         writel(0x303C0000, &ccm->CCGR1);        /* GPT, OCRAM */
 542         writel(0x00FFFCC0, &ccm->CCGR2);        /* IPMUX, I2C1, I2C3 */
 543         writel(0x3F300030, &ccm->CCGR3);        /* OCRAM, MMDC, ENET */
 544         writel(0x0000C003, &ccm->CCGR4);        /* PCI, PL301 */
 545         writel(0x0F0330C3, &ccm->CCGR5);        /* UART, ROM */
 546         writel(0x00000F00, &ccm->CCGR6);        /* SDHI4, EIM */
 547 }
 548
 549 static void vining2000_spl_dram_init(void)
 550 {
 551         struct mx6_ddr_sysinfo sysinfo = {
 552                 .dsize          = mem_ddr.width / 32,
 553                 .cs_density     = 24,
 554                 .ncs            = 1,
 555                 .cs1_mirror     = 0,
 556                 .rtt_wr         = 1,    /* RTT_wr = RZQ/4 */
 557                 .rtt_nom        = 1,    /* RTT_Nom = RZQ/4 */
 558                 .walat          = 1,    /* Write additional latency */
 559                 .ralat          = 5,    /* Read additional latency */
 560                 .mif3_mode      = 3,    /* Command prediction working mode */
 561                 .bi_on          = 1,    /* Bank interleaving enabled */
 562                 .sde_to_rst     = 0x10, /* 14 cycles, 200us (JEDEC default) */
 563                 .rst_to_cke     = 0x23, /* 33 cycles, 500us (JEDEC default) */
 564                 .ddr_type       = DDR_TYPE_DDR3,
 565                 .refsel         = 1,    /* Refresh cycles at 32KHz */
 566                 .refr           = 7,    /* 8 refresh commands per refresh cycle */
 567         };
 568
 569         mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 570         mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
 571
 572         /* Perform DDR DRAM calibration */
 573         udelay(100);
 574         mmdc_do_write_level_calibration(&sysinfo);
 575         mmdc_do_dqs_calibration(&sysinfo);
 576 }
 577
 578 void board_init_f(ulong dummy)
 579 {
 580         /* setup AIPS and disable watchdog */
 581         arch_cpu_init();
 582
 583         ccgr_init();
 584
 585         /* iomux setup */
 586         vining2000_spl_setup_iomux_pcie();
 587         vining2000_spl_setup_iomux_uart();
 588
 589         /* setup GP timer */
 590         timer_init();
 591
 592         /* reset the PCIe device */
 593         gpio_set_value(IMX_GPIO_NR(4, 6), 1);
 594         udelay(50);
 595         gpio_set_value(IMX_GPIO_NR(4, 6), 0);
 596
 597         /* UART clocks enabled and gd valid - init serial console */
 598         preloader_console_init();
 599
 600         /* DDR initialization */
 601         vining2000_spl_dram_init();
 602
 603         /* Clear the BSS. */
 604         memset(__bss_start, 0, __bss_end - __bss_start);
 605
 606         /* load/boot image from boot device */
 607         board_init_r(NULL, 0);
 608 }
 609 #endif