3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
5 * Copyright 2004 Freescale Semiconductor.
6 * (C) Copyright 2002,2003, Motorola Inc.
7 * Xianghua Xiao, (X.Xiao@motorola.com)
9 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/processor.h>
33 #include <asm/immap_85xx.h>
37 #include <fdt_support.h>
40 #include "upm_table.h"
42 DECLARE_GLOBAL_DATA_PTR;
44 extern flash_info_t flash_info[]; /* FLASH chips info */
46 void local_bus_init (void);
47 ulong flash_get_size (ulong base, int banknum);
51 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
55 char *s = getenv("serial#");
57 puts("Board: Socrates");
65 /* Check the PCI_clk sel bit */
66 if (in_be32(&gur->porpllsr) & (1<<15)) {
68 f = CONFIG_SYS_CLK_FREQ;
71 f = CONFIG_PCI_CLK_FREQ;
73 printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
75 printf ("PCI1: disabled\n");
79 * Initialize local bus.
85 int misc_init_r (void)
87 volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
90 * Adjust flash start and offset to detected values
92 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
93 gd->bd->bi_flashoffset = 0;
96 * Check if boot FLASH isn't max size
98 if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
99 memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
100 memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
103 * Re-check to get correct base address
105 flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
109 * Check if only one FLASH bank is available
111 if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
116 * Re-do flash protection upon new addresses
118 flash_protect (FLAG_PROTECT_CLEAR,
119 gd->bd->bi_flashstart, 0xffffffff,
120 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
122 /* Monitor protection ON by default */
123 flash_protect (FLAG_PROTECT_SET,
124 CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
125 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
127 /* Environment protection ON by default */
128 flash_protect (FLAG_PROTECT_SET,
130 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
131 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
133 /* Redundant environment protection ON by default */
134 flash_protect (FLAG_PROTECT_SET,
136 CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
137 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
144 * Initialize Local Bus
146 void local_bus_init (void)
148 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
149 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
153 uint lcrr = CFG_LBC_LCRR;
155 get_sys_info (&sysinfo);
156 clkdiv = lbc->lcrr & 0x0f;
157 lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv;
159 /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
161 lcrr &= ~LCRR_DBYP; /* DLL Enabled */
163 lcrr |= LCRR_DBYP; /* DLL Bypass */
165 out_be32 (&lbc->lcrr, lcrr);
166 asm ("sync;isync;msync");
168 out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
169 out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
170 out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
171 out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
173 /* Init UPMA for FPGA access */
174 out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
175 upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
178 #if defined(CONFIG_PCI)
180 * Initialize PCI Devices, report devices found.
183 #ifndef CONFIG_PCI_PNP
184 static struct pci_config_table pci_mpc85xxads_config_table[] = {
185 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
186 PCI_IDSEL_NUMBER, PCI_ANY_ID,
187 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
190 PCI_COMMAND_MASTER}},
196 static struct pci_controller hose = {
197 #ifndef CONFIG_PCI_PNP
198 config_table:pci_mpc85xxads_config_table,
202 #endif /* CONFIG_PCI */
205 void pci_init_board (void)
208 pci_mpc85xx_init (&hose);
209 #endif /* CONFIG_PCI */
212 #ifdef CONFIG_BOARD_EARLY_INIT_R
213 int board_early_init_r (void)
215 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
217 /* set and reset the GPIO pin 2 which will reset the W83782G chip */
218 out_8((unsigned char*)&gur->gpoutdr, 0x3F );
219 out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
221 out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
225 #endif /* CONFIG_BOARD_EARLY_INIT_R */
227 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
229 ft_board_setup(void *blob, bd_t *bd)
234 ft_cpu_setup(blob, bd);
236 /* Fixup NOR FLASH mapping */
237 val[i++] = 0; /* chip select number */
238 val[i++] = 0; /* always 0 */
239 val[i++] = gd->bd->bi_flashstart;
240 val[i++] = gd->bd->bi_flashsize;
242 /* Fixup FPGA mapping */
243 val[i++] = 3; /* chip select number */
244 val[i++] = 0; /* always 0 */
245 val[i++] = CFG_FPGA_BASE;
246 val[i++] = CFG_FPGA_SIZE;
248 rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
249 val, i * sizeof(u32), 1);
251 printf("Unable to update localbus ranges, err=%s\n",
254 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */