1 // SPDX-License-Identifier: GPL-2.0+
4 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003, Motorola Inc.
8 * Xianghua Xiao, (X.Xiao@motorola.com)
10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
14 #include <clock_legacy.h>
19 #include <asm/global_data.h>
20 #include <asm/processor.h>
21 #include <asm/immap_85xx.h>
24 #include <linux/delay.h>
25 #include <linux/libfdt.h>
26 #include <fdt_support.h>
29 #include "upm_table.h"
31 DECLARE_GLOBAL_DATA_PTR;
33 extern flash_info_t flash_info[]; /* FLASH chips info */
35 void local_bus_init (void);
36 ulong flash_get_size (ulong base, int banknum);
40 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
43 int i = env_get_f("serial#", buf, sizeof(buf));
48 puts("Board: Socrates");
55 #if defined(CONFIG_PCI)
56 /* Check the PCI_clk sel bit */
57 if (in_be32(&gur->porpllsr) & (1<<15)) {
59 f = get_board_sys_clk();
62 /* PCI is clocked by the external source at 33 MHz */
65 printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
67 printf ("PCI1: disabled\n");
71 * Initialize local bus.
77 int misc_init_r (void)
80 * Adjust flash start and offset to detected values
82 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
83 gd->bd->bi_flashoffset = 0;
86 * Check if boot FLASH isn't max size
88 if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
89 set_lbc_or(0, gd->bd->bi_flashstart |
90 (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
91 set_lbc_br(0, gd->bd->bi_flashstart |
92 (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
95 * Re-check to get correct base address
97 flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
101 * Check if only one FLASH bank is available
103 if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
108 * Re-do flash protection upon new addresses
110 flash_protect(FLAG_PROTECT_CLEAR,
111 gd->bd->bi_flashstart, 0xffffffff,
112 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
114 /* Monitor protection ON by default */
115 flash_protect(FLAG_PROTECT_SET,
116 CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE +
117 monitor_flash_len - 1,
118 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
120 /* Environment protection ON by default */
121 flash_protect(FLAG_PROTECT_SET,
123 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
124 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
126 /* Redundant environment protection ON by default */
127 flash_protect(FLAG_PROTECT_SET,
128 CONFIG_ENV_ADDR_REDUND,
129 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
130 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
139 * Initialize Local Bus
141 void local_bus_init (void)
143 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
144 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
148 uint lcrr = CONFIG_SYS_LBC_LCRR;
150 get_sys_info (&sysinfo);
151 clkdiv = lbc->lcrr & LCRR_CLKDIV;
152 lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
154 /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
156 lcrr &= ~LCRR_DBYP; /* DLL Enabled */
158 lcrr |= LCRR_DBYP; /* DLL Bypass */
160 out_be32 (&lbc->lcrr, lcrr);
161 asm ("sync;isync;msync");
163 out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
164 out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
165 out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
166 out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
168 /* Init UPMA for FPGA access */
169 out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
170 upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA) / sizeof(int));
172 /* Init UPMB for Lime controller access */
173 out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
174 upmconfig(UPMB, (uint *)UPMTableB, sizeof(UPMTableB) / sizeof(int));
177 #ifdef CONFIG_BOARD_EARLY_INIT_R
178 int board_early_init_r (void)
180 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
182 /* set and reset the GPIO pin 2 which will reset the W83782G chip */
183 out_8((unsigned char*)&gur->gpoutdr, 0x3F );
184 out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
186 out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
190 #endif /* CONFIG_BOARD_EARLY_INIT_R */
192 #ifdef CONFIG_OF_BOARD_SETUP
193 int ft_board_setup(void *blob, struct bd_info *bd)
198 ft_cpu_setup(blob, bd);
200 /* Fixup NOR FLASH mapping */
201 val[i++] = 0; /* chip select number */
202 val[i++] = 0; /* always 0 */
203 val[i++] = gd->bd->bi_flashstart;
204 val[i++] = gd->bd->bi_flashsize;
206 /* Fixup FPGA mapping */
207 val[i++] = 3; /* chip select number */
208 val[i++] = 0; /* always 0 */
209 val[i++] = CONFIG_SYS_FPGA_BASE;
210 val[i++] = CONFIG_SYS_FPGA_SIZE;
212 rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
213 val, i * sizeof(u32), 1);
215 printf("Unable to update localbus ranges, err=%s\n",
220 #endif /* CONFIG_OF_BOARD_SETUP */
222 #if defined(CONFIG_OF_SEPARATE)
223 void *board_fdt_blob_setup(int *err)
228 fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE);
229 if (fdt_magic(fw_dtb) != FDT_MAGIC) {
230 printf("DTB is not passed via %x\n", (u32)fw_dtb);
239 int get_serial_clock(void)