1 // SPDX-License-Identifier: GPL-2.0+
4 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003, Motorola Inc.
8 * Xianghua Xiao, (X.Xiao@motorola.com)
10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
14 #include <clock_legacy.h>
19 #include <asm/global_data.h>
20 #include <asm/processor.h>
21 #include <asm/immap_85xx.h>
24 #include <linux/delay.h>
25 #include <linux/libfdt.h>
26 #include <fdt_support.h>
29 #include "upm_table.h"
31 DECLARE_GLOBAL_DATA_PTR;
33 void local_bus_init (void);
34 ulong flash_get_size (ulong base, int banknum);
38 volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
41 int i = env_get_f("serial#", buf, sizeof(buf));
46 puts("Board: Socrates");
53 #if defined(CONFIG_PCI)
54 /* Check the PCI_clk sel bit */
55 if (in_be32(&gur->porpllsr) & (1<<15)) {
57 f = get_board_sys_clk();
60 /* PCI is clocked by the external source at 33 MHz */
63 printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
65 printf ("PCI1: disabled\n");
69 * Initialize local bus.
75 int misc_init_r (void)
78 * Adjust flash start and offset to detected values
80 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
81 gd->bd->bi_flashoffset = 0;
84 * Check if boot FLASH isn't max size
86 if (gd->bd->bi_flashsize < (0 - CFG_SYS_FLASH0)) {
87 set_lbc_or(0, gd->bd->bi_flashstart |
88 (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
89 set_lbc_br(0, gd->bd->bi_flashstart |
90 (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
93 * Re-check to get correct base address
95 flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
99 * Check if only one FLASH bank is available
101 if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CFG_SYS_FLASH0)) {
106 * Re-do flash protection upon new addresses
108 flash_protect(FLAG_PROTECT_CLEAR,
109 gd->bd->bi_flashstart, 0xffffffff,
110 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
112 /* Monitor protection ON by default */
113 flash_protect(FLAG_PROTECT_SET,
114 CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE +
115 monitor_flash_len - 1,
116 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
118 /* Environment protection ON by default */
119 flash_protect(FLAG_PROTECT_SET,
121 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
122 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
124 /* Redundant environment protection ON by default */
125 flash_protect(FLAG_PROTECT_SET,
126 CONFIG_ENV_ADDR_REDUND,
127 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
128 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
137 * Initialize Local Bus
139 void local_bus_init (void)
141 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
142 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
146 uint lcrr = CFG_SYS_LBC_LCRR;
148 get_sys_info (&sysinfo);
149 clkdiv = lbc->lcrr & LCRR_CLKDIV;
150 lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
152 /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
154 lcrr &= ~LCRR_DBYP; /* DLL Enabled */
156 lcrr |= LCRR_DBYP; /* DLL Bypass */
158 out_be32 (&lbc->lcrr, lcrr);
159 asm ("sync;isync;msync");
161 out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
162 out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
163 out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
164 out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
166 /* Init UPMA for FPGA access */
167 out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
168 upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA) / sizeof(int));
170 /* Init UPMB for Lime controller access */
171 out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
172 upmconfig(UPMB, (uint *)UPMTableB, sizeof(UPMTableB) / sizeof(int));
175 #ifdef CONFIG_BOARD_EARLY_INIT_R
176 int board_early_init_r (void)
178 volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
180 /* set and reset the GPIO pin 2 which will reset the W83782G chip */
181 out_8((unsigned char*)&gur->gpoutdr, 0x3F );
182 out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
184 out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
188 #endif /* CONFIG_BOARD_EARLY_INIT_R */
190 #ifdef CONFIG_OF_BOARD_SETUP
191 int ft_board_setup(void *blob, struct bd_info *bd)
196 ft_cpu_setup(blob, bd);
198 /* Fixup NOR FLASH mapping */
199 val[i++] = 0; /* chip select number */
200 val[i++] = 0; /* always 0 */
201 val[i++] = gd->bd->bi_flashstart;
202 val[i++] = gd->bd->bi_flashsize;
204 /* Fixup FPGA mapping */
205 val[i++] = 3; /* chip select number */
206 val[i++] = 0; /* always 0 */
207 val[i++] = CFG_SYS_FPGA_BASE;
208 val[i++] = CFG_SYS_FPGA_SIZE;
210 rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
211 val, i * sizeof(u32), 1);
213 printf("Unable to update localbus ranges, err=%s\n",
218 #endif /* CONFIG_OF_BOARD_SETUP */
220 int get_serial_clock(void)