1 // SPDX-License-Identifier: GPL-2.0+
4 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003, Motorola Inc.
8 * Xianghua Xiao, (X.Xiao@motorola.com)
10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
14 #include <clock_legacy.h>
19 #include <asm/global_data.h>
20 #include <asm/processor.h>
21 #include <asm/immap_85xx.h>
24 #include <linux/delay.h>
25 #include <linux/libfdt.h>
26 #include <fdt_support.h>
31 #include "upm_table.h"
33 DECLARE_GLOBAL_DATA_PTR;
35 extern flash_info_t flash_info[]; /* FLASH chips info */
36 extern GraphicDevice mb862xx;
38 void local_bus_init (void);
39 ulong flash_get_size (ulong base, int banknum);
43 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
46 int i = env_get_f("serial#", buf, sizeof(buf));
51 puts("Board: Socrates");
58 #if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI)
59 /* Check the PCI_clk sel bit */
60 if (in_be32(&gur->porpllsr) & (1<<15)) {
62 f = CONFIG_SYS_CLK_FREQ;
65 f = CONFIG_PCI_CLK_FREQ;
67 printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
69 printf ("PCI1: disabled\n");
73 * Initialize local bus.
79 int misc_init_r (void)
82 * Adjust flash start and offset to detected values
84 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
85 gd->bd->bi_flashoffset = 0;
88 * Check if boot FLASH isn't max size
90 if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
91 set_lbc_or(0, gd->bd->bi_flashstart |
92 (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
93 set_lbc_br(0, gd->bd->bi_flashstart |
94 (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
97 * Re-check to get correct base address
99 flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
103 * Check if only one FLASH bank is available
105 if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
110 * Re-do flash protection upon new addresses
112 flash_protect(FLAG_PROTECT_CLEAR,
113 gd->bd->bi_flashstart, 0xffffffff,
114 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
116 /* Monitor protection ON by default */
117 flash_protect(FLAG_PROTECT_SET,
118 CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE +
119 monitor_flash_len - 1,
120 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
122 /* Environment protection ON by default */
123 flash_protect(FLAG_PROTECT_SET,
125 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
126 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
128 /* Redundant environment protection ON by default */
129 flash_protect(FLAG_PROTECT_SET,
130 CONFIG_ENV_ADDR_REDUND,
131 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
132 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
135 #if defined(CONFIG_DM_PCI)
143 * Initialize Local Bus
145 void local_bus_init (void)
147 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
148 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
152 uint lcrr = CONFIG_SYS_LBC_LCRR;
154 get_sys_info (&sysinfo);
155 clkdiv = lbc->lcrr & LCRR_CLKDIV;
156 lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
158 /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
160 lcrr &= ~LCRR_DBYP; /* DLL Enabled */
162 lcrr |= LCRR_DBYP; /* DLL Bypass */
164 out_be32 (&lbc->lcrr, lcrr);
165 asm ("sync;isync;msync");
167 out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
168 out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
169 out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
170 out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
172 /* Init UPMA for FPGA access */
173 out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
174 upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA) / sizeof(int));
176 /* Init UPMB for Lime controller access */
177 out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
178 upmconfig(UPMB, (uint *)UPMTableB, sizeof(UPMTableB) / sizeof(int));
181 #ifdef CONFIG_BOARD_EARLY_INIT_R
182 int board_early_init_r (void)
184 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
186 /* set and reset the GPIO pin 2 which will reset the W83782G chip */
187 out_8((unsigned char*)&gur->gpoutdr, 0x3F );
188 out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
190 out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
194 #endif /* CONFIG_BOARD_EARLY_INIT_R */
196 #ifdef CONFIG_OF_BOARD_SETUP
197 int ft_board_setup(void *blob, struct bd_info *bd)
202 ft_cpu_setup(blob, bd);
204 /* Fixup NOR FLASH mapping */
205 val[i++] = 0; /* chip select number */
206 val[i++] = 0; /* always 0 */
207 val[i++] = gd->bd->bi_flashstart;
208 val[i++] = gd->bd->bi_flashsize;
210 #if defined(CONFIG_VIDEO_MB862xx)
211 if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
212 /* Fixup LIME mapping */
213 val[i++] = 2; /* chip select number */
214 val[i++] = 0; /* always 0 */
215 val[i++] = CONFIG_SYS_LIME_BASE;
216 val[i++] = CONFIG_SYS_LIME_SIZE;
220 /* Fixup FPGA mapping */
221 val[i++] = 3; /* chip select number */
222 val[i++] = 0; /* always 0 */
223 val[i++] = CONFIG_SYS_FPGA_BASE;
224 val[i++] = CONFIG_SYS_FPGA_SIZE;
226 rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
227 val, i * sizeof(u32), 1);
229 printf("Unable to update localbus ranges, err=%s\n",
234 #endif /* CONFIG_OF_BOARD_SETUP */
236 #if defined(CONFIG_OF_SEPARATE)
237 void *board_fdt_blob_setup(void)
241 fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE);
242 if (fdt_magic(fw_dtb) != FDT_MAGIC) {
243 printf("DTB is not passed via %x\n", (u32)fw_dtb);
251 int get_serial_clock(void)