1 // SPDX-License-Identifier: GPL-2.0+
4 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
9 #include <asm/processor.h>
10 #include <asm/immap_85xx.h>
11 #include <fsl_ddr_sdram.h>
12 #include <asm/processor.h>
14 #include <spd_sdram.h>
15 #include <linux/delay.h>
18 #if !defined(CONFIG_SPD_EEPROM)
20 * Autodetect onboard DDR SDRAM on 85xx platforms
22 * NOTE: Some of the hardcoded values are hardware dependant,
23 * so this should be extended for other future boards
26 phys_size_t fixed_sdram(void)
28 struct ccsr_ddr __iomem *ddr =
29 (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
32 * Disable memory controller.
37 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
38 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
39 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
40 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
41 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
42 ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
43 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
44 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
45 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL;
47 asm ("sync;isync;msync");
50 ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG;
51 asm ("sync; isync; msync");
54 if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
56 * OK, size detected -> all done
58 return CONFIG_SYS_SDRAM_SIZE<<20;
61 return 0; /* nothing found ! */
65 #if defined(CONFIG_SYS_DRAM_TEST)
68 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
69 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
72 printf ("SDRAM test phase 1:\n");
73 for (p = pstart; p < pend; p++)
76 for (p = pstart; p < pend; p++) {
77 if (*p != 0xaaaaaaaa) {
78 printf ("SDRAM test fails at: %08x\n", (uint) p);
83 printf ("SDRAM test phase 2:\n");
84 for (p = pstart; p < pend; p++)
87 for (p = pstart; p < pend; p++) {
88 if (*p != 0x55555555) {
89 printf ("SDRAM test fails at: %08x\n", (uint) p);
94 printf ("SDRAM test passed.\n");