board/socionext/developerbox/developerbox.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * u-boot/board/socionext/developerbox/developerbox.c
   4  *
   5  * Copyright (C) 2016-2017 Socionext Inc.
   6  * Copyright (C) 2021 Linaro Ltd.
   7  */
   8 #include <asm/types.h>
   9 #include <asm/armv8/mmu.h>
  10 #include <asm/global_data.h>
  11 #include <asm/io.h>
  12 #include <common.h>
  13 #include <efi.h>
  14 #include <efi_loader.h>
  15 #include <env_internal.h>
  16 #include <fdt_support.h>
  17 #include <log.h>
  18
  19 #include <linux/kernel.h>
  20
  21 #if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
  22 struct efi_fw_image fw_images[] = {
  23         {
  24                 .image_type_id = DEVELOPERBOX_UBOOT_IMAGE_GUID,
  25                 .fw_name = u"DEVELOPERBOX-UBOOT",
  26                 .image_index = 1,
  27         },
  28         {
  29                 .image_type_id = DEVELOPERBOX_FIP_IMAGE_GUID,
  30                 .fw_name = u"DEVELOPERBOX-FIP",
  31                 .image_index = 2,
  32         },
  33         {
  34                 .image_type_id = DEVELOPERBOX_OPTEE_IMAGE_GUID,
  35                 .fw_name = u"DEVELOPERBOX-OPTEE",
  36                 .image_index = 3,
  37         },
  38 };
  39
  40 struct efi_capsule_update_info update_info = {
  41         .dfu_string = "mtd nor1=u-boot.bin raw 200000 100000;"
  42                         "fip.bin raw 180000 78000;"
  43                         "optee.bin raw 500000 100000",
  44         .images = fw_images,
  45 };
  46
  47 u8 num_image_type_guids = ARRAY_SIZE(fw_images);
  48 #endif /* EFI_HAVE_CAPSULE_SUPPORT */
  49
  50 static struct mm_region sc2a11_mem_map[] = {
  51         {
  52                 .virt = 0x0UL,
  53                 .phys = 0x0UL,
  54                 .size = 0x80000000UL,
  55                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  56                          PTE_BLOCK_OUTER_SHARE
  57         }, {
  58                 /* 1st DDR block */
  59                 .virt = 0x80000000UL,
  60                 .phys = 0x80000000UL,
  61                 .size = PHYS_SDRAM_SIZE,
  62                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  63                          PTE_BLOCK_OUTER_SHARE
  64         }, {
  65                 /* 2nd DDR place holder */
  66                 0,
  67         }, {
  68                 /* 3rd DDR place holder */
  69                 0,
  70         }, {
  71                 /* List terminator */
  72                 0,
  73         }
  74 };
  75
  76 struct mm_region *mem_map = sc2a11_mem_map;
  77
  78 #define DDR_REGION_INDEX(i)     (1 + (i))
  79 #define MAX_DDR_REGIONS         3
  80
  81 struct draminfo_entry {
  82         u64     base;
  83         u64     size;
  84 };
  85
  86 struct draminfo {
  87         u32     nr_regions;
  88         u32     reserved;
  89         struct draminfo_entry   entry[3];
  90 };
  91
  92 struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
  93
  94 DECLARE_GLOBAL_DATA_PTR;
  95
  96 #define LOAD_OFFSET 0x100
  97
  98 /* SCBM System MMU is used for eMMC and NETSEC */
  99 #define SCBM_SMMU_ADDR                          (0x52e00000UL)
 100 #define SMMU_SCR0_OFFS                          (0x0)
 101 #define SMMU_SCR0_SHCFG_INNER                   (0x2 << 22)
 102 #define SMMU_SCR0_MTCFG                         (0x1 << 20)
 103 #define SMMU_SCR0_MEMATTR_INNER_OUTER_WB        (0xf << 16)
 104
 105 static void synquacer_setup_scbm_smmu(void)
 106 {
 107         writel(SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTER_WB,
 108                SCBM_SMMU_ADDR + SMMU_SCR0_OFFS);
 109 }
 110
 111 /*
 112  * Miscellaneous platform dependent initialisations
 113  */
 114 int board_init(void)
 115 {
 116         gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET;
 117
 118         gd->env_addr = (ulong)&default_environment[0];
 119
 120         synquacer_setup_scbm_smmu();
 121
 122         return 0;
 123 }
 124
 125 int ft_board_setup(void *blob, struct bd_info *bd)
 126 {
 127         /* Remove SPI NOR and I2C0 for making DT compatible with EDK2 */
 128         fdt_del_node_and_alias(blob, "spi_nor");
 129         fdt_del_node_and_alias(blob, "i2c0");
 130
 131         return 0;
 132 }
 133
 134 /*
 135  * DRAM configuration
 136  */
 137
 138 int dram_init(void)
 139 {
 140         struct draminfo_entry *ent = synquacer_draminfo->entry;
 141         struct mm_region *mr;
 142         int i, ri;
 143
 144         if (synquacer_draminfo->nr_regions < 1) {
 145                 log_err("Failed to get correct DRAM information\n");
 146                 return -1;
 147         }
 148
 149         /*
 150          * U-Boot RAM size must be under the first DRAM region so that it doesn't
 151          * access secure memory which is at the end of the first DRAM region.
 152          */
 153         gd->ram_size = ent[0].size;
 154
 155         /* Update memory region maps */
 156         for (i = 0; i < synquacer_draminfo->nr_regions; i++) {
 157                 if (i >= MAX_DDR_REGIONS)
 158                         break;
 159
 160                 ri = DDR_REGION_INDEX(i);
 161                 mem_map[ri].phys = ent[i].base;
 162                 mem_map[ri].size = ent[i].size;
 163                 if (i == 0)
 164                         continue;
 165
 166                 mr = &mem_map[DDR_REGION_INDEX(0)];
 167                 mem_map[ri].virt = mr->virt + mr->size;
 168                 mem_map[ri].attrs = mr->attrs;
 169         }
 170
 171         return 0;
 172 }
 173
 174 int dram_init_banksize(void)
 175 {
 176         struct draminfo_entry *ent = synquacer_draminfo->entry;
 177         int i;
 178
 179         for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
 180                 if (i < synquacer_draminfo->nr_regions) {
 181                         debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base);
 182                         gd->bd->bi_dram[i].start = ent[i].base;
 183                         gd->bd->bi_dram[i].size = ent[i].size;
 184                 }
 185         }
 186
 187         return 0;
 188 }
 189
 190 int print_cpuinfo(void)
 191 {
 192         printf("CPU:   SC2A11:Cortex-A53 MPCore 24cores\n");
 193         return 0;
 194 }