board/siemens/pxm2/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board functions for TI AM335X based pxm2 board
   4  * (C) Copyright 2013 Siemens Schweiz AG
   5  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
   6  *
   7  * Based on:
   8  * u-boot:/board/ti/am335x/board.c
   9  *
  10  * Board functions for TI AM335X based boards
  11  *
  12  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  13  */
  14
  15 #include <common.h>
  16 #include <env.h>
  17 #include <errno.h>
  18 #include <init.h>
  19 #include <log.h>
  20 #include <malloc.h>
  21 #include <net.h>
  22 #include <spl.h>
  23 #include <asm/arch/cpu.h>
  24 #include <asm/arch/hardware.h>
  25 #include <asm/arch/omap.h>
  26 #include <asm/arch/ddr_defs.h>
  27 #include <asm/arch/clock.h>
  28 #include <asm/arch/gpio.h>
  29 #include <asm/arch/mmc_host_def.h>
  30 #include <asm/arch/sys_proto.h>
  31 #include <asm/io.h>
  32 #include <asm/emif.h>
  33 #include <asm/gpio.h>
  34 #include <i2c.h>
  35 #include <miiphy.h>
  36 #include <cpsw.h>
  37 #include <watchdog.h>
  38 #include "board.h"
  39 #include "../common/factoryset.h"
  40 #include "pmic.h"
  41 #include <nand.h>
  42 #include <bmp_layout.h>
  43
  44 #ifdef CONFIG_SPL_BUILD
  45 static void board_init_ddr(void)
  46 {
  47 struct emif_regs pxm2_ddr3_emif_reg_data = {
  48         .sdram_config = 0x41805332,
  49         .sdram_tim1 = 0x666b3c9,
  50         .sdram_tim2 = 0x243631ca,
  51         .sdram_tim3 = 0x33f,
  52         .emif_ddr_phy_ctlr_1 = 0x100005,
  53         .zq_config = 0,
  54         .ref_ctrl = 0x81a,
  55 };
  56
  57 struct ddr_data pxm2_ddr3_data = {
  58         .datardsratio0 = 0x81204812,
  59         .datawdsratio0 = 0,
  60         .datafwsratio0 = 0x8020080,
  61         .datawrsratio0 = 0x4010040,
  62 };
  63
  64 struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
  65         .cmd0csratio = 0x80,
  66         .cmd0iclkout = 0,
  67         .cmd1csratio = 0x80,
  68         .cmd1iclkout = 0,
  69         .cmd2csratio = 0x80,
  70         .cmd2iclkout = 0,
  71 };
  72
  73 const struct ctrl_ioregs ioregs = {
  74         .cm0ioctl               = DDR_IOCTRL_VAL,
  75         .cm1ioctl               = DDR_IOCTRL_VAL,
  76         .cm2ioctl               = DDR_IOCTRL_VAL,
  77         .dt0ioctl               = DDR_IOCTRL_VAL,
  78         .dt1ioctl               = DDR_IOCTRL_VAL,
  79 };
  80
  81         config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
  82                    &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
  83 }
  84
  85 /*
  86  * voltage switching for MPU frequency switching.
  87  * @module = mpu - 0, core - 1
  88  * @vddx_op_vol_sel = vdd voltage to set
  89  */
  90
  91 #define MPU     0
  92 #define CORE    1
  93
  94 int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
  95 {
  96         uchar buf[4];
  97         unsigned int reg_offset;
  98
  99         if (module == MPU)
 100                 reg_offset = PMIC_VDD1_OP_REG;
 101         else
 102                 reg_offset = PMIC_VDD2_OP_REG;
 103
 104         /* Select VDDx OP   */
 105         if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 106                 return 1;
 107
 108         buf[0] &= ~PMIC_OP_REG_CMD_MASK;
 109
 110         if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 111                 return 1;
 112
 113         /* Configure VDDx OP  Voltage */
 114         if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 115                 return 1;
 116
 117         buf[0] &= ~PMIC_OP_REG_SEL_MASK;
 118         buf[0] |= vddx_op_vol_sel;
 119
 120         if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 121                 return 1;
 122
 123         if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 124                 return 1;
 125
 126         if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
 127                 return 1;
 128
 129         return 0;
 130 }
 131
 132 #define OSC     (V_OSCK/1000000)
 133
 134 const struct dpll_params dpll_mpu_pxm2 = {
 135                 720, OSC-1, 1, -1, -1, -1, -1};
 136
 137 void spl_siemens_board_init(void)
 138 {
 139         uchar buf[4];
 140         /*
 141          * pxm2 PMIC code.  All boards currently want an MPU voltage
 142          * of 1.2625V and CORE voltage of 1.1375V to operate at
 143          * 720MHz.
 144          */
 145         if (i2c_probe(PMIC_CTRL_I2C_ADDR))
 146                 return;
 147
 148         /* VDD1/2 voltage selection register access by control i/f */
 149         if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
 150                 return;
 151
 152         buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
 153
 154         if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
 155                 return;
 156
 157         /* Frequency switching for OPP 120 */
 158         if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
 159             voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
 160                 printf("voltage update failed\n");
 161         }
 162 }
 163 #endif /* if def CONFIG_SPL_BUILD */
 164
 165 int read_eeprom(void)
 166 {
 167         /* nothing ToDo here for this board */
 168
 169         return 0;
 170 }
 171
 172 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 173         (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
 174 static void cpsw_control(int enabled)
 175 {
 176         /* VTP can be added here */
 177
 178         return;
 179 }
 180
 181 static struct cpsw_slave_data cpsw_slaves[] = {
 182         {
 183                 .slave_reg_ofs  = 0x208,
 184                 .sliver_reg_ofs = 0xd80,
 185                 .phy_addr       = 0,
 186                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 187         },
 188         {
 189                 .slave_reg_ofs  = 0x308,
 190                 .sliver_reg_ofs = 0xdc0,
 191                 .phy_addr       = 1,
 192                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 193         },
 194 };
 195
 196 static struct cpsw_platform_data cpsw_data = {
 197         .mdio_base              = CPSW_MDIO_BASE,
 198         .cpsw_base              = CPSW_BASE,
 199         .mdio_div               = 0xff,
 200         .channels               = 4,
 201         .cpdma_reg_ofs          = 0x800,
 202         .slaves                 = 1,
 203         .slave_data             = cpsw_slaves,
 204         .ale_reg_ofs            = 0xd00,
 205         .ale_entries            = 1024,
 206         .host_port_reg_ofs      = 0x108,
 207         .hw_stats_reg_ofs       = 0x900,
 208         .bd_ram_ofs             = 0x2000,
 209         .mac_control            = (1 << 5),
 210         .control                = cpsw_control,
 211         .host_port_num          = 0,
 212         .version                = CPSW_CTRL_VERSION_2,
 213 };
 214 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 215
 216 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 217         (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
 218 int board_eth_init(struct bd_info *bis)
 219 {
 220         int n = 0;
 221 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 222         (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
 223         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 224 #ifdef CONFIG_FACTORYSET
 225         int rv;
 226         if (!is_valid_ethaddr(factory_dat.mac))
 227                 printf("Error: no valid mac address\n");
 228         else
 229                 eth_env_set_enetaddr("ethaddr", factory_dat.mac);
 230 #endif /* #ifdef CONFIG_FACTORYSET */
 231
 232         /* Set rgmii mode and enable rmii clock to be sourced from chip */
 233         writel(RGMII_MODE_ENABLE  | RGMII_INT_DELAY, &cdev->miisel);
 234
 235         rv = cpsw_register(&cpsw_data);
 236         if (rv < 0)
 237                 printf("Error %d registering CPSW switch\n", rv);
 238         else
 239                 n += rv;
 240 #endif
 241         return n;
 242 }
 243 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 244
 245 #ifdef CONFIG_BOARD_LATE_INIT
 246 int board_late_init(void)
 247 {
 248         int ret;
 249
 250         omap_nand_switch_ecc(1, 8);
 251
 252 #ifdef CONFIG_FACTORYSET
 253         if (factory_dat.asn[0] != 0) {
 254                 char tmp[2 * MAX_STRING_LENGTH + 2];
 255
 256                 if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0)
 257                         factory_dat.pxm50 = 1;
 258                 else
 259                         factory_dat.pxm50 = 0;
 260                 sprintf(tmp, "%s_%s", factory_dat.asn,
 261                         factory_dat.comp_version);
 262                 ret = env_set("boardid", tmp);
 263                 if (ret)
 264                         printf("error setting board id\n");
 265         } else {
 266                 factory_dat.pxm50 = 1;
 267                 ret = env_set("boardid", "PXM50_1.0");
 268                 if (ret)
 269                         printf("error setting board id\n");
 270         }
 271         debug("PXM50: %d\n", factory_dat.pxm50);
 272 #endif
 273
 274         return 0;
 275 }
 276 #endif
 277
 278 #include "../common/board.c"