2 * Board functions for TI AM335X based pxm2 board
3 * (C) Copyright 2013 Siemens Schweiz AG
4 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * u-boot:/board/ti/am335x/board.c
9 * Board functions for TI AM335X based boards
11 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
13 * SPDX-License-Identifier: GPL-2.0+
19 #include <asm/arch/cpu.h>
20 #include <asm/arch/hardware.h>
21 #include <asm/arch/omap.h>
22 #include <asm/arch/ddr_defs.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/mmc_host_def.h>
26 #include <asm/arch/sys_proto.h>
27 #include "../../../drivers/video/da8xx-fb.h"
36 #include "../common/factoryset.h"
39 #include <bmp_layout.h>
41 DECLARE_GLOBAL_DATA_PTR;
43 #ifdef CONFIG_SPL_BUILD
44 static void board_init_ddr(void)
46 struct emif_regs pxm2_ddr3_emif_reg_data = {
47 .sdram_config = 0x41805332,
48 .sdram_tim1 = 0x666b3c9,
49 .sdram_tim2 = 0x243631ca,
51 .emif_ddr_phy_ctlr_1 = 0x100005,
56 struct ddr_data pxm2_ddr3_data = {
57 .datardsratio0 = 0x81204812,
59 .datafwsratio0 = 0x8020080,
60 .datawrsratio0 = 0x4010040,
63 struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
72 config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data,
73 &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
77 * voltage switching for MPU frequency switching.
78 * @module = mpu - 0, core - 1
79 * @vddx_op_vol_sel = vdd voltage to set
85 int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
88 unsigned int reg_offset;
91 reg_offset = PMIC_VDD1_OP_REG;
93 reg_offset = PMIC_VDD2_OP_REG;
96 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
99 buf[0] &= ~PMIC_OP_REG_CMD_MASK;
101 if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
104 /* Configure VDDx OP Voltage */
105 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
108 buf[0] &= ~PMIC_OP_REG_SEL_MASK;
109 buf[0] |= vddx_op_vol_sel;
111 if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
114 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
117 if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
123 #define OSC (V_OSCK/1000000)
125 const struct dpll_params dpll_mpu_pxm2 = {
126 720, OSC-1, 1, -1, -1, -1, -1};
128 void spl_siemens_board_init(void)
132 * pxm2 PMIC code. All boards currently want an MPU voltage
133 * of 1.2625V and CORE voltage of 1.1375V to operate at
136 if (i2c_probe(PMIC_CTRL_I2C_ADDR))
139 /* VDD1/2 voltage selection register access by control i/f */
140 if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
143 buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
145 if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
148 /* Frequency switching for OPP 120 */
149 if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
150 voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
151 printf("voltage update failed\n");
154 #endif /* if def CONFIG_SPL_BUILD */
156 int read_eeprom(void)
158 /* nothing ToDo here for this board */
163 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
164 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
165 static void cpsw_control(int enabled)
167 /* VTP can be added here */
172 static struct cpsw_slave_data cpsw_slaves[] = {
174 .slave_reg_ofs = 0x208,
175 .sliver_reg_ofs = 0xd80,
177 .phy_if = PHY_INTERFACE_MODE_RMII,
180 .slave_reg_ofs = 0x308,
181 .sliver_reg_ofs = 0xdc0,
183 .phy_if = PHY_INTERFACE_MODE_RMII,
187 static struct cpsw_platform_data cpsw_data = {
188 .mdio_base = CPSW_MDIO_BASE,
189 .cpsw_base = CPSW_BASE,
192 .cpdma_reg_ofs = 0x800,
194 .slave_data = cpsw_slaves,
195 .ale_reg_ofs = 0xd00,
197 .host_port_reg_ofs = 0x108,
198 .hw_stats_reg_ofs = 0x900,
199 .bd_ram_ofs = 0x2000,
200 .mac_control = (1 << 5),
201 .control = cpsw_control,
203 .version = CPSW_CTRL_VERSION_2,
205 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
207 #if defined(CONFIG_DRIVER_TI_CPSW) || \
208 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
209 int board_eth_init(bd_t *bis)
212 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
213 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
214 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
215 #ifdef CONFIG_FACTORYSET
217 if (!is_valid_ether_addr(factory_dat.mac))
218 printf("Error: no valid mac address\n");
220 eth_setenv_enetaddr("ethaddr", factory_dat.mac);
221 #endif /* #ifdef CONFIG_FACTORYSET */
223 /* Set rgmii mode and enable rmii clock to be sourced from chip */
224 writel(RGMII_MODE_ENABLE , &cdev->miisel);
226 rv = cpsw_register(&cpsw_data);
228 printf("Error %d registering CPSW switch\n", rv);
234 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
236 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
237 static struct da8xx_panel lcd_panels[] = {
238 /* AUO G156XW01 V1 */
240 .name = "AUO_G156XW01_V1",
252 /* AUO B101EVN06 V0 */
254 .name = "AUO_B101EVN06_V0",
267 * Settings from factoryset
271 .name = "factoryset",
285 static const struct display_panel disp_panel = {
292 static const struct lcd_ctrl_config lcd_cfg = {
302 .invert_line_clock = 1,
303 .invert_frm_clock = 1,
309 static int set_gpio(int gpio, int state)
311 gpio_request(gpio, "temp");
312 gpio_direction_output(gpio, state);
313 gpio_set_value(gpio, state);
318 static int enable_backlight(void)
320 set_gpio(BOARD_LCD_POWER, 1);
321 set_gpio(BOARD_BACK_LIGHT, 1);
322 set_gpio(BOARD_TOUCH_POWER, 1);
326 static int enable_pwm(void)
328 struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE;
329 struct pwmss_ecap_regs *ecap;
330 int ticks = PWM_TICKS;
333 ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
335 setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
336 /* TimeStam Counter register */
337 writel(0xdb9, &ecap->tsctr);
339 writel(ticks - 1, &ecap->cap3);
340 writel(ticks - 1, &ecap->cap1);
341 setbits_le16(&ecap->ecctl2,
342 (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0));
344 writel(duty, &ecap->cap2);
345 writel(duty, &ecap->cap4);
347 setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
351 static struct dpll_regs dpll_lcd_regs = {
352 .cm_clkmode_dpll = CM_WKUP + 0x98,
353 .cm_idlest_dpll = CM_WKUP + 0x48,
354 .cm_clksel_dpll = CM_WKUP + 0x54,
357 /* no console on this board */
358 int board_cfb_skip(void)
363 #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
364 #define PLL_GET_N(v) (v & 0x7f)
366 static int get_clk(struct dpll_regs *dpll_regs)
372 val = readl(dpll_regs->cm_clksel_dpll);
375 f = (m * V_OSCK) / n;
382 return get_clk(&dpll_lcd_regs);
385 static int conf_disp_pll(int m, int n)
387 struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
388 struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
389 struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
391 u32 *const clk_domains[] = {
395 u32 *const clk_modules_explicit_en[] = {
397 &cmper->lcdcclkstctrl,
398 &cmper->epwmss0clkctrl,
401 do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
402 writel(0x0, &cmdpll->clklcdcpixelclk);
404 do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
409 static int board_video_init(void)
411 conf_disp_pll(24, 1);
412 if (factory_dat.pxm50)
413 da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
415 da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);
423 #include "../common/board.c"