board/siemens/pxm2/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board functions for TI AM335X based pxm2 board
   4  * (C) Copyright 2013 Siemens Schweiz AG
   5  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
   6  *
   7  * Based on:
   8  * u-boot:/board/ti/am335x/board.c
   9  *
  10  * Board functions for TI AM335X based boards
  11  *
  12  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  13  */
  14
  15 #include <common.h>
  16 #include <env.h>
  17 #include <errno.h>
  18 #include <init.h>
  19 #include <log.h>
  20 #include <malloc.h>
  21 #include <net.h>
  22 #include <spl.h>
  23 #include <asm/arch/cpu.h>
  24 #include <asm/arch/hardware.h>
  25 #include <asm/arch/omap.h>
  26 #include <asm/arch/ddr_defs.h>
  27 #include <asm/arch/clock.h>
  28 #include <asm/arch/gpio.h>
  29 #include <asm/arch/mmc_host_def.h>
  30 #include <asm/arch/sys_proto.h>
  31 #include "../../../drivers/video/da8xx-fb.h"
  32 #include <asm/io.h>
  33 #include <asm/emif.h>
  34 #include <asm/gpio.h>
  35 #include <i2c.h>
  36 #include <miiphy.h>
  37 #include <cpsw.h>
  38 #include <watchdog.h>
  39 #include "board.h"
  40 #include "../common/factoryset.h"
  41 #include "pmic.h"
  42 #include <nand.h>
  43 #include <bmp_layout.h>
  44
  45 #ifdef CONFIG_SPL_BUILD
  46 static void board_init_ddr(void)
  47 {
  48 struct emif_regs pxm2_ddr3_emif_reg_data = {
  49         .sdram_config = 0x41805332,
  50         .sdram_tim1 = 0x666b3c9,
  51         .sdram_tim2 = 0x243631ca,
  52         .sdram_tim3 = 0x33f,
  53         .emif_ddr_phy_ctlr_1 = 0x100005,
  54         .zq_config = 0,
  55         .ref_ctrl = 0x81a,
  56 };
  57
  58 struct ddr_data pxm2_ddr3_data = {
  59         .datardsratio0 = 0x81204812,
  60         .datawdsratio0 = 0,
  61         .datafwsratio0 = 0x8020080,
  62         .datawrsratio0 = 0x4010040,
  63 };
  64
  65 struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
  66         .cmd0csratio = 0x80,
  67         .cmd0iclkout = 0,
  68         .cmd1csratio = 0x80,
  69         .cmd1iclkout = 0,
  70         .cmd2csratio = 0x80,
  71         .cmd2iclkout = 0,
  72 };
  73
  74 const struct ctrl_ioregs ioregs = {
  75         .cm0ioctl               = DDR_IOCTRL_VAL,
  76         .cm1ioctl               = DDR_IOCTRL_VAL,
  77         .cm2ioctl               = DDR_IOCTRL_VAL,
  78         .dt0ioctl               = DDR_IOCTRL_VAL,
  79         .dt1ioctl               = DDR_IOCTRL_VAL,
  80 };
  81
  82         config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
  83                    &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
  84 }
  85
  86 /*
  87  * voltage switching for MPU frequency switching.
  88  * @module = mpu - 0, core - 1
  89  * @vddx_op_vol_sel = vdd voltage to set
  90  */
  91
  92 #define MPU     0
  93 #define CORE    1
  94
  95 int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
  96 {
  97         uchar buf[4];
  98         unsigned int reg_offset;
  99
 100         if (module == MPU)
 101                 reg_offset = PMIC_VDD1_OP_REG;
 102         else
 103                 reg_offset = PMIC_VDD2_OP_REG;
 104
 105         /* Select VDDx OP   */
 106         if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 107                 return 1;
 108
 109         buf[0] &= ~PMIC_OP_REG_CMD_MASK;
 110
 111         if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 112                 return 1;
 113
 114         /* Configure VDDx OP  Voltage */
 115         if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 116                 return 1;
 117
 118         buf[0] &= ~PMIC_OP_REG_SEL_MASK;
 119         buf[0] |= vddx_op_vol_sel;
 120
 121         if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 122                 return 1;
 123
 124         if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 125                 return 1;
 126
 127         if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
 128                 return 1;
 129
 130         return 0;
 131 }
 132
 133 #define OSC     (V_OSCK/1000000)
 134
 135 const struct dpll_params dpll_mpu_pxm2 = {
 136                 720, OSC-1, 1, -1, -1, -1, -1};
 137
 138 void spl_siemens_board_init(void)
 139 {
 140         uchar buf[4];
 141         /*
 142          * pxm2 PMIC code.  All boards currently want an MPU voltage
 143          * of 1.2625V and CORE voltage of 1.1375V to operate at
 144          * 720MHz.
 145          */
 146         if (i2c_probe(PMIC_CTRL_I2C_ADDR))
 147                 return;
 148
 149         /* VDD1/2 voltage selection register access by control i/f */
 150         if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
 151                 return;
 152
 153         buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
 154
 155         if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
 156                 return;
 157
 158         /* Frequency switching for OPP 120 */
 159         if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
 160             voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
 161                 printf("voltage update failed\n");
 162         }
 163 }
 164 #endif /* if def CONFIG_SPL_BUILD */
 165
 166 int read_eeprom(void)
 167 {
 168         /* nothing ToDo here for this board */
 169
 170         return 0;
 171 }
 172
 173 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 174         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 175 static void cpsw_control(int enabled)
 176 {
 177         /* VTP can be added here */
 178
 179         return;
 180 }
 181
 182 static struct cpsw_slave_data cpsw_slaves[] = {
 183         {
 184                 .slave_reg_ofs  = 0x208,
 185                 .sliver_reg_ofs = 0xd80,
 186                 .phy_addr       = 0,
 187                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 188         },
 189         {
 190                 .slave_reg_ofs  = 0x308,
 191                 .sliver_reg_ofs = 0xdc0,
 192                 .phy_addr       = 1,
 193                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 194         },
 195 };
 196
 197 static struct cpsw_platform_data cpsw_data = {
 198         .mdio_base              = CPSW_MDIO_BASE,
 199         .cpsw_base              = CPSW_BASE,
 200         .mdio_div               = 0xff,
 201         .channels               = 4,
 202         .cpdma_reg_ofs          = 0x800,
 203         .slaves                 = 1,
 204         .slave_data             = cpsw_slaves,
 205         .ale_reg_ofs            = 0xd00,
 206         .ale_entries            = 1024,
 207         .host_port_reg_ofs      = 0x108,
 208         .hw_stats_reg_ofs       = 0x900,
 209         .bd_ram_ofs             = 0x2000,
 210         .mac_control            = (1 << 5),
 211         .control                = cpsw_control,
 212         .host_port_num          = 0,
 213         .version                = CPSW_CTRL_VERSION_2,
 214 };
 215 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 216
 217 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 218         (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
 219 int board_eth_init(bd_t *bis)
 220 {
 221         int n = 0;
 222 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 223         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 224         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 225 #ifdef CONFIG_FACTORYSET
 226         int rv;
 227         if (!is_valid_ethaddr(factory_dat.mac))
 228                 printf("Error: no valid mac address\n");
 229         else
 230                 eth_env_set_enetaddr("ethaddr", factory_dat.mac);
 231 #endif /* #ifdef CONFIG_FACTORYSET */
 232
 233         /* Set rgmii mode and enable rmii clock to be sourced from chip */
 234         writel(RGMII_MODE_ENABLE  | RGMII_INT_DELAY, &cdev->miisel);
 235
 236         rv = cpsw_register(&cpsw_data);
 237         if (rv < 0)
 238                 printf("Error %d registering CPSW switch\n", rv);
 239         else
 240                 n += rv;
 241 #endif
 242         return n;
 243 }
 244 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 245
 246 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
 247 static struct da8xx_panel lcd_panels[] = {
 248         /* AUO G156XW01 V1 */
 249         [0] = {
 250                 .name = "AUO_G156XW01_V1",
 251                 .width = 1376,
 252                 .height = 768,
 253                 .hfp = 14,
 254                 .hbp = 64,
 255                 .hsw = 56,
 256                 .vfp = 1,
 257                 .vbp = 28,
 258                 .vsw = 3,
 259                 .pxl_clk = 60000000,
 260                 .invert_pxl_clk = 0,
 261         },
 262         /* AUO B101EVN06 V0 */
 263         [1] = {
 264                 .name = "AUO_B101EVN06_V0",
 265                 .width = 1280,
 266                 .height = 800,
 267                 .hfp = 52,
 268                 .hbp = 84,
 269                 .hsw = 36,
 270                 .vfp = 3,
 271                 .vbp = 14,
 272                 .vsw = 6,
 273                 .pxl_clk = 60000000,
 274                 .invert_pxl_clk = 0,
 275         },
 276         /*
 277          * Settings from factoryset
 278          * stored in EEPROM
 279          */
 280         [2] = {
 281                 .name = "factoryset",
 282                 .width = 0,
 283                 .height = 0,
 284                 .hfp = 0,
 285                 .hbp = 0,
 286                 .hsw = 0,
 287                 .vfp = 0,
 288                 .vbp = 0,
 289                 .vsw = 0,
 290                 .pxl_clk = 60000000,
 291                 .invert_pxl_clk = 0,
 292         },
 293 };
 294
 295 static const struct display_panel disp_panel = {
 296         WVGA,
 297         32,
 298         16,
 299         COLOR_ACTIVE,
 300 };
 301
 302 static const struct lcd_ctrl_config lcd_cfg = {
 303         &disp_panel,
 304         .ac_bias                = 255,
 305         .ac_bias_intrpt         = 0,
 306         .dma_burst_sz           = 16,
 307         .bpp                    = 32,
 308         .fdd                    = 0x80,
 309         .tft_alt_mode           = 0,
 310         .stn_565_mode           = 0,
 311         .mono_8bit_mode         = 0,
 312         .invert_line_clock      = 1,
 313         .invert_frm_clock       = 1,
 314         .sync_edge              = 0,
 315         .sync_ctrl              = 1,
 316         .raster_order           = 0,
 317 };
 318
 319 static int set_gpio(int gpio, int state)
 320 {
 321         gpio_request(gpio, "temp");
 322         gpio_direction_output(gpio, state);
 323         gpio_set_value(gpio, state);
 324         gpio_free(gpio);
 325         return 0;
 326 }
 327
 328 static int enable_backlight(void)
 329 {
 330         set_gpio(BOARD_LCD_POWER, 1);
 331         set_gpio(BOARD_BACK_LIGHT, 1);
 332         set_gpio(BOARD_TOUCH_POWER, 1);
 333         return 0;
 334 }
 335
 336 static int enable_pwm(void)
 337 {
 338         struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE;
 339         struct pwmss_ecap_regs *ecap;
 340         int ticks = PWM_TICKS;
 341         int duty = PWM_DUTY;
 342
 343         ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
 344         /* enable clock */
 345         setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
 346         /* TimeStam Counter register */
 347         writel(0xdb9, &ecap->tsctr);
 348         /* config period */
 349         writel(ticks - 1, &ecap->cap3);
 350         writel(ticks - 1, &ecap->cap1);
 351         setbits_le16(&ecap->ecctl2,
 352                      (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0));
 353         /* config duty */
 354         writel(duty, &ecap->cap2);
 355         writel(duty, &ecap->cap4);
 356         /* start */
 357         setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
 358         return 0;
 359 }
 360
 361 static struct dpll_regs dpll_lcd_regs = {
 362         .cm_clkmode_dpll = CM_WKUP + 0x98,
 363         .cm_idlest_dpll = CM_WKUP + 0x48,
 364         .cm_clksel_dpll = CM_WKUP + 0x54,
 365 };
 366
 367 /* no console on this board */
 368 int board_cfb_skip(void)
 369 {
 370         return 1;
 371 }
 372
 373 #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
 374 #define PLL_GET_N(v) (v & 0x7f)
 375
 376 static int get_clk(struct dpll_regs *dpll_regs)
 377 {
 378         unsigned int val;
 379         unsigned int m, n;
 380         int f = 0;
 381
 382         val = readl(dpll_regs->cm_clksel_dpll);
 383         m = PLL_GET_M(val);
 384         n = PLL_GET_N(val);
 385         f = (m * V_OSCK) / n;
 386
 387         return f;
 388 };
 389
 390 int clk_get(int clk)
 391 {
 392         return get_clk(&dpll_lcd_regs);
 393 };
 394
 395 static int conf_disp_pll(int m, int n)
 396 {
 397         struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 398         struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
 399         struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
 400
 401         u32 *const clk_domains[] = {
 402                 &cmper->lcdclkctrl,
 403                 0
 404         };
 405         u32 *const clk_modules_explicit_en[] = {
 406                 &cmper->lcdclkctrl,
 407                 &cmper->lcdcclkstctrl,
 408                 &cmper->epwmss0clkctrl,
 409                 0
 410         };
 411         do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
 412         writel(0x0, &cmdpll->clklcdcpixelclk);
 413
 414         do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
 415
 416         return 0;
 417 }
 418
 419 static int board_video_init(void)
 420 {
 421         conf_disp_pll(24, 1);
 422         if (factory_dat.pxm50)
 423                 da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
 424         else
 425                 da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);
 426
 427         enable_pwm();
 428         enable_backlight();
 429
 430         return 0;
 431 }
 432 #endif
 433
 434 #ifdef CONFIG_BOARD_LATE_INIT
 435 int board_late_init(void)
 436 {
 437         int ret;
 438
 439         omap_nand_switch_ecc(1, 8);
 440
 441 #ifdef CONFIG_FACTORYSET
 442         if (factory_dat.asn[0] != 0) {
 443                 char tmp[2 * MAX_STRING_LENGTH + 2];
 444
 445                 if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0)
 446                         factory_dat.pxm50 = 1;
 447                 else
 448                         factory_dat.pxm50 = 0;
 449                 sprintf(tmp, "%s_%s", factory_dat.asn,
 450                         factory_dat.comp_version);
 451                 ret = env_set("boardid", tmp);
 452                 if (ret)
 453                         printf("error setting board id\n");
 454         } else {
 455                 factory_dat.pxm50 = 1;
 456                 ret = env_set("boardid", "PXM50_1.0");
 457                 if (ret)
 458                         printf("error setting board id\n");
 459         }
 460         debug("PXM50: %d\n", factory_dat.pxm50);
 461 #endif
 462
 463         return 0;
 464 }
 465 #endif
 466
 467 #include "../common/board.c"