board/siemens/draco/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board functions for TI AM335X based draco board
   4  * (C) Copyright 2013 Siemens Schweiz AG
   5  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
   6  *
   7  * Based on:
   8  *
   9  * Board functions for TI AM335X based boards
  10  * u-boot:/board/ti/am335x/board.c
  11  *
  12  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  13  */
  14
  15 #include <common.h>
  16 #include <command.h>
  17 #include <env.h>
  18 #include <errno.h>
  19 #include <init.h>
  20 #include <net.h>
  21 #include <spl.h>
  22 #include <asm/arch/cpu.h>
  23 #include <asm/arch/hardware.h>
  24 #include <asm/arch/omap.h>
  25 #include <asm/arch/ddr_defs.h>
  26 #include <asm/arch/clock.h>
  27 #include <asm/arch/gpio.h>
  28 #include <asm/arch/mmc_host_def.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <asm/arch/mem.h>
  31 #include <asm/io.h>
  32 #include <asm/emif.h>
  33 #include <asm/gpio.h>
  34 #include <i2c.h>
  35 #include <miiphy.h>
  36 #include <cpsw.h>
  37 #include <watchdog.h>
  38 #include <linux/delay.h>
  39 #include "board.h"
  40 #include "../common/factoryset.h"
  41 #include <nand.h>
  42
  43 #ifdef CONFIG_SPL_BUILD
  44 static struct draco_baseboard_id __section(".data") settings;
  45
  46 #if DDR_PLL_FREQ == 303
  47 #if !defined(CONFIG_TARGET_ETAMIN)
  48 /* Default@303MHz-i0 */
  49 const struct ddr3_data ddr3_default = {
  50         0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
  51         0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32,
  52         0x0000093B, 0x0000014A,
  53         "default name @303MHz           \0",
  54         "default marking                \0",
  55 };
  56 #else
  57 /* etamin board */
  58 const struct ddr3_data ddr3_default = {
  59         0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
  60         0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
  61         0x0000093B, 0x0000018A,
  62         "test-etamin                    \0",
  63         "generic-8Gbit                  \0",
  64 };
  65 #endif
  66 #elif DDR_PLL_FREQ == 400
  67 /* Default@400MHz-i0 */
  68 const struct ddr3_data ddr3_default = {
  69         0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
  70         0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
  71         0x00000618, 0x0000014A,
  72         "default name @400MHz           \0",
  73         "default marking                \0",
  74 };
  75 #endif
  76
  77 static void set_default_ddr3_timings(void)
  78 {
  79         printf("Set default DDR3 settings\n");
  80         settings.ddr3 = ddr3_default;
  81 }
  82
  83 static void print_ddr3_timings(void)
  84 {
  85         printf("\nDDR3\n");
  86         printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
  87         printf("device:\t\t%s\n", settings.ddr3.manu_name);
  88         printf("marking:\t%s\n", settings.ddr3.manu_marking);
  89         printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom",
  90                "default", "diff");
  91         PRINTARGS(magic);
  92         PRINTARGS(version);
  93         PRINTARGS(ddr3_sratio);
  94         PRINTARGS(iclkout);
  95
  96         PRINTARGS(dt0rdsratio0);
  97         PRINTARGS(dt0wdsratio0);
  98         PRINTARGS(dt0fwsratio0);
  99         PRINTARGS(dt0wrsratio0);
 100
 101         PRINTARGS(sdram_tim1);
 102         PRINTARGS(sdram_tim2);
 103         PRINTARGS(sdram_tim3);
 104
 105         PRINTARGS(emif_ddr_phy_ctlr_1);
 106
 107         PRINTARGS(sdram_config);
 108         PRINTARGS(ref_ctrl);
 109         PRINTARGS(ioctr_val);
 110 }
 111
 112 static void print_chip_data(void)
 113 {
 114         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 115         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 116         printf("\nCPU BOARD\n");
 117         printf("device: \t'%s'\n", settings.chip.sdevname);
 118         printf("hw version: \t'%s'\n", settings.chip.shwver);
 119         printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m);
 120 }
 121 #endif /* CONFIG_SPL_BUILD */
 122
 123 #define AM335X_NAND_ECC_MASK 0x0f
 124 #define AM335X_NAND_ECC_TYPE_16 0x02
 125
 126 static int ecc_type;
 127
 128 struct am335x_nand_geometry {
 129         u32 magic;
 130         u8 nand_geo_addr;
 131         u8 nand_geo_page;
 132         u8 nand_bus;
 133 };
 134
 135 #define EEPROM_ADDR             0x50
 136 #define EEPROM_ADDR_DDR3        0x90
 137 #define EEPROM_ADDR_CHIP        0x120
 138
 139 static int draco_read_nand_geometry(void)
 140 {
 141         struct am335x_nand_geometry geo;
 142
 143         /* Read NAND geometry */
 144         if (i2c_read(EEPROM_ADDR, 0x80, 2,
 145                      (uchar *)&geo, sizeof(struct am335x_nand_geometry))) {
 146                 printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
 147                 return -EIO;
 148         }
 149         if (geo.magic != 0xa657b310) {
 150                 printf("%s: bad magic: %x\n", __func__, geo.magic);
 151                 return -EFAULT;
 152         }
 153         if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16)
 154                 ecc_type = 16;
 155         else
 156                 ecc_type = 8;
 157
 158         return 0;
 159 }
 160
 161 /*
 162  * Read header information from EEPROM into global structure.
 163  */
 164 static int read_eeprom(void)
 165 {
 166         /* Check if baseboard eeprom is available */
 167         if (i2c_probe(EEPROM_ADDR)) {
 168                 printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
 169                 return 1;
 170         }
 171
 172 #ifdef CONFIG_SPL_BUILD
 173         /* Read Siemens eeprom data (DDR3) */
 174         if (i2c_read(EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
 175                      (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
 176                 printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
 177                 set_default_ddr3_timings();
 178         }
 179         /* Read Siemens eeprom data (CHIP) */
 180         if (i2c_read(EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
 181                      (uchar *)&settings.chip, sizeof(settings.chip)))
 182                 printf("Could not read chip settings\n");
 183
 184         if (ddr3_default.magic == settings.ddr3.magic &&
 185             ddr3_default.version == settings.ddr3.version) {
 186                 printf("Using DDR3 settings from EEPROM\n");
 187         } else {
 188                 if (ddr3_default.magic != settings.ddr3.magic)
 189                         printf("Warning: No valid DDR3 data in eeprom.\n");
 190                 if (ddr3_default.version != settings.ddr3.version)
 191                         printf("Warning: DDR3 data version does not match.\n");
 192
 193                 printf("Using default settings\n");
 194                 set_default_ddr3_timings();
 195         }
 196
 197         if (MAGIC_CHIP == settings.chip.magic)
 198                 print_chip_data();
 199         else
 200                 printf("Warning: No chip data in eeprom\n");
 201
 202         print_ddr3_timings();
 203
 204         return draco_read_nand_geometry();
 205 #endif
 206         return 0;
 207 }
 208
 209 #ifdef CONFIG_SPL_BUILD
 210 static void board_init_ddr(void)
 211 {
 212 struct emif_regs draco_ddr3_emif_reg_data = {
 213         .zq_config = 0x50074BE4,
 214 };
 215
 216 struct ddr_data draco_ddr3_data = {
 217 };
 218
 219 struct cmd_control draco_ddr3_cmd_ctrl_data = {
 220 };
 221
 222 struct ctrl_ioregs draco_ddr3_ioregs = {
 223 };
 224
 225         /* pass values from eeprom */
 226         draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
 227         draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
 228         draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
 229         draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
 230                 settings.ddr3.emif_ddr_phy_ctlr_1;
 231         draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
 232         draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
 233         draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
 234
 235         draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
 236         draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
 237         draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
 238         draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
 239
 240         draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
 241         draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
 242         draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
 243         draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
 244         draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
 245         draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
 246
 247         draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
 248         draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
 249         draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
 250         draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
 251         draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
 252
 253         config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
 254                    &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
 255 }
 256
 257 static void spl_siemens_board_init(void)
 258 {
 259         return;
 260 }
 261 #endif /* if def CONFIG_SPL_BUILD */
 262
 263 #ifdef CONFIG_BOARD_LATE_INIT
 264 int board_late_init(void)
 265 {
 266         int ret;
 267
 268         ret = draco_read_nand_geometry();
 269         if (ret != 0)
 270                 return ret;
 271
 272         nand_curr_device = 0;
 273         omap_nand_switch_ecc(1, ecc_type);
 274 #ifdef CONFIG_TARGET_ETAMIN
 275         nand_curr_device = 1;
 276         omap_nand_switch_ecc(1, ecc_type);
 277 #endif
 278 #ifdef CONFIG_FACTORYSET
 279         /* Set ASN in environment*/
 280         if (factory_dat.asn[0] != 0) {
 281                 env_set("dtb_name", (char *)factory_dat.asn);
 282         } else {
 283                 /* dtb suffix gets added in load script */
 284                 env_set("dtb_name", "am335x-draco");
 285         }
 286 #else
 287         env_set("dtb_name", "am335x-draco");
 288 #endif
 289
 290         return 0;
 291 }
 292 #endif
 293
 294 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 295         (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
 296 static void cpsw_control(int enabled)
 297 {
 298         /* VTP can be added here */
 299
 300         return;
 301 }
 302
 303 static struct cpsw_slave_data cpsw_slaves[] = {
 304         {
 305                 .slave_reg_ofs  = 0x208,
 306                 .sliver_reg_ofs = 0xd80,
 307                 .phy_addr       = 0,
 308                 .phy_if         = PHY_INTERFACE_MODE_MII,
 309         },
 310 };
 311
 312 static struct cpsw_platform_data cpsw_data = {
 313         .mdio_base              = CPSW_MDIO_BASE,
 314         .cpsw_base              = CPSW_BASE,
 315         .mdio_div               = 0xff,
 316         .channels               = 4,
 317         .cpdma_reg_ofs          = 0x800,
 318         .slaves                 = 1,
 319         .slave_data             = cpsw_slaves,
 320         .ale_reg_ofs            = 0xd00,
 321         .ale_entries            = 1024,
 322         .host_port_reg_ofs      = 0x108,
 323         .hw_stats_reg_ofs       = 0x900,
 324         .bd_ram_ofs             = 0x2000,
 325         .mac_control            = (1 << 5),
 326         .control                = cpsw_control,
 327         .host_port_num          = 0,
 328         .version                = CPSW_CTRL_VERSION_2,
 329 };
 330
 331 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 332         (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
 333 int board_eth_init(struct bd_info *bis)
 334 {
 335         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 336         int n = 0;
 337         int rv;
 338
 339         factoryset_env_set();
 340
 341         /* Set rgmii mode and enable rmii clock to be sourced from chip */
 342         writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
 343
 344         rv = cpsw_register(&cpsw_data);
 345         if (rv < 0)
 346                 printf("Error %d registering CPSW switch\n", rv);
 347         else
 348                 n += rv;
 349         return n;
 350 }
 351
 352 static int do_switch_reset(struct cmd_tbl *cmdtp, int flag, int argc,
 353                            char *const argv[])
 354 {
 355         /* Reset SMSC LAN9303 switch for default configuration */
 356         gpio_request(GPIO_LAN9303_NRST, "nRST");
 357         gpio_direction_output(GPIO_LAN9303_NRST, 0);
 358         /* assert active low reset for 200us */
 359         udelay(200);
 360         gpio_set_value(GPIO_LAN9303_NRST, 1);
 361
 362         return 0;
 363 };
 364
 365 U_BOOT_CMD(
 366         switch_rst, CONFIG_SYS_MAXARGS, 1,      do_switch_reset,
 367         "Reset LAN9303 switch via its reset pin",
 368         ""
 369 );
 370 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 371 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 372
 373 #if CONFIG_IS_ENABLED(NAND_CS_INIT)
 374 #define ETAMIN_NAND_GPMC_CONFIG1        0x00000800
 375 #define ETAMIN_NAND_GPMC_CONFIG2        0x001e1e00
 376 #define ETAMIN_NAND_GPMC_CONFIG3        0x001e1e00
 377 #define ETAMIN_NAND_GPMC_CONFIG4        0x16051807
 378 #define ETAMIN_NAND_GPMC_CONFIG5        0x00151e1e
 379 #define ETAMIN_NAND_GPMC_CONFIG6        0x16000f80
 380
 381 /* GPMC definitions for second nand cs1 */
 382 static const u32 gpmc_nand_config[] = {
 383         ETAMIN_NAND_GPMC_CONFIG1,
 384         ETAMIN_NAND_GPMC_CONFIG2,
 385         ETAMIN_NAND_GPMC_CONFIG3,
 386         ETAMIN_NAND_GPMC_CONFIG4,
 387         ETAMIN_NAND_GPMC_CONFIG5,
 388         ETAMIN_NAND_GPMC_CONFIG6,
 389         /*CONFIG7- computed as params */
 390 };
 391
 392 static void board_nand_cs_init(void)
 393 {
 394         enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1],
 395                               0x18000000, GPMC_SIZE_16M);
 396 }
 397 #endif
 398
 399 #include "../common/board.c"