board/siemens/draco/board.c

   1 /*
   2  * Board functions for TI AM335X based draco board
   3  * (C) Copyright 2013 Siemens Schweiz AG
   4  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  *
   8  * Board functions for TI AM335X based boards
   9  * u-boot:/board/ti/am335x/board.c
  10  *
  11  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <common.h>
  17 #include <errno.h>
  18 #include <spl.h>
  19 #include <asm/arch/cpu.h>
  20 #include <asm/arch/hardware.h>
  21 #include <asm/arch/omap.h>
  22 #include <asm/arch/ddr_defs.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/mmc_host_def.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <asm/io.h>
  28 #include <asm/emif.h>
  29 #include <asm/gpio.h>
  30 #include <i2c.h>
  31 #include <miiphy.h>
  32 #include <cpsw.h>
  33 #include <watchdog.h>
  34 #include "board.h"
  35 #include "../common/factoryset.h"
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #ifdef CONFIG_SPL_BUILD
  40 static struct draco_baseboard_id __attribute__((section(".data"))) settings;
  41
  42 #if DDR_PLL_FREQ == 303
  43 /* Default@303MHz-i0 */
  44 const struct ddr3_data ddr3_default = {
  45         0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
  46         0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32,
  47         0x0000093B, 0x0000014A,
  48         "default name @303MHz           \0",
  49         "default marking                \0",
  50 };
  51 #elif DDR_PLL_FREQ == 400
  52 /* Default@400MHz-i0 */
  53 const struct ddr3_data ddr3_default = {
  54         0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
  55         0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
  56         0x00000618, 0x0000014A,
  57         "default name @400MHz           \0",
  58         "default marking                \0",
  59 };
  60 #endif
  61
  62 static void set_default_ddr3_timings(void)
  63 {
  64         printf("Set default DDR3 settings\n");
  65         settings.ddr3 = ddr3_default;
  66 }
  67
  68 static void print_ddr3_timings(void)
  69 {
  70         printf("\nDDR3\n");
  71         printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
  72         printf("device:\t\t%s\n", settings.ddr3.manu_name);
  73         printf("marking:\t%s\n", settings.ddr3.manu_marking);
  74         printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom",
  75                "default", "diff");
  76         PRINTARGS(magic);
  77         PRINTARGS(version);
  78         PRINTARGS(ddr3_sratio);
  79         PRINTARGS(iclkout);
  80
  81         PRINTARGS(dt0rdsratio0);
  82         PRINTARGS(dt0wdsratio0);
  83         PRINTARGS(dt0fwsratio0);
  84         PRINTARGS(dt0wrsratio0);
  85
  86         PRINTARGS(sdram_tim1);
  87         PRINTARGS(sdram_tim2);
  88         PRINTARGS(sdram_tim3);
  89
  90         PRINTARGS(emif_ddr_phy_ctlr_1);
  91
  92         PRINTARGS(sdram_config);
  93         PRINTARGS(ref_ctrl);
  94         PRINTARGS(ioctr_val);
  95 }
  96
  97 static void print_chip_data(void)
  98 {
  99         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 100         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 101         printf("\nCPU BOARD\n");
 102         printf("device: \t'%s'\n", settings.chip.sdevname);
 103         printf("hw version: \t'%s'\n", settings.chip.shwver);
 104         printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m);
 105 }
 106 #endif /* CONFIG_SPL_BUILD */
 107
 108 #define AM335X_NAND_ECC_MASK 0x0f
 109 #define AM335X_NAND_ECC_TYPE_16 0x02
 110
 111 static int ecc_type;
 112
 113 struct am335x_nand_geometry {
 114         u32 magic;
 115         u8 nand_geo_addr;
 116         u8 nand_geo_page;
 117         u8 nand_bus;
 118 };
 119
 120 static int draco_read_nand_geometry(void)
 121 {
 122         struct am335x_nand_geometry geo;
 123
 124         /* Read NAND geometry */
 125         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2,
 126                      (uchar *)&geo, sizeof(struct am335x_nand_geometry))) {
 127                 printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
 128                 return -EIO;
 129         }
 130         if (geo.magic != 0xa657b310) {
 131                 printf("%s: bad magic: %x\n", __func__, geo.magic);
 132                 return -EFAULT;
 133         }
 134         if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16)
 135                 ecc_type = 16;
 136         else
 137                 ecc_type = 8;
 138
 139         return 0;
 140 }
 141
 142 /*
 143  * Read header information from EEPROM into global structure.
 144  */
 145 static int read_eeprom(void)
 146 {
 147         /* Check if baseboard eeprom is available */
 148         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
 149                 printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
 150                 return 1;
 151         }
 152
 153 #ifdef CONFIG_SPL_BUILD
 154         /* Read Siemens eeprom data (DDR3) */
 155         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
 156                      (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
 157                 printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
 158                 set_default_ddr3_timings();
 159         }
 160         /* Read Siemens eeprom data (CHIP) */
 161         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
 162                      (uchar *)&settings.chip, sizeof(settings.chip)))
 163                 printf("Could not read chip settings\n");
 164
 165         if (ddr3_default.magic == settings.ddr3.magic &&
 166             ddr3_default.version == settings.ddr3.version) {
 167                 printf("Using DDR3 settings from EEPROM\n");
 168         } else {
 169                 if (ddr3_default.magic != settings.ddr3.magic)
 170                         printf("Warning: No valid DDR3 data in eeprom.\n");
 171                 if (ddr3_default.version != settings.ddr3.version)
 172                         printf("Warning: DDR3 data version does not match.\n");
 173
 174                 printf("Using default settings\n");
 175                 set_default_ddr3_timings();
 176         }
 177
 178         if (MAGIC_CHIP == settings.chip.magic)
 179                 print_chip_data();
 180         else
 181                 printf("Warning: No chip data in eeprom\n");
 182
 183         print_ddr3_timings();
 184
 185         return draco_read_nand_geometry();
 186 #endif
 187         return 0;
 188 }
 189
 190 #ifdef CONFIG_SPL_BUILD
 191 static void board_init_ddr(void)
 192 {
 193 struct emif_regs draco_ddr3_emif_reg_data = {
 194         .zq_config = 0x50074BE4,
 195 };
 196
 197 struct ddr_data draco_ddr3_data = {
 198 };
 199
 200 struct cmd_control draco_ddr3_cmd_ctrl_data = {
 201 };
 202
 203 struct ctrl_ioregs draco_ddr3_ioregs = {
 204 };
 205
 206         /* pass values from eeprom */
 207         draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
 208         draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
 209         draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
 210         draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
 211                 settings.ddr3.emif_ddr_phy_ctlr_1;
 212         draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
 213         draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
 214
 215         draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
 216         draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
 217         draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
 218         draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
 219
 220         draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
 221         draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
 222         draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
 223         draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
 224         draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
 225         draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
 226
 227         draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
 228         draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
 229         draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
 230         draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
 231         draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
 232
 233         config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
 234                    &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
 235 }
 236
 237 static void spl_siemens_board_init(void)
 238 {
 239         return;
 240 }
 241 #endif /* if def CONFIG_SPL_BUILD */
 242
 243 #ifdef CONFIG_BOARD_LATE_INIT
 244 int board_late_init(void)
 245 {
 246         int ret;
 247
 248         ret = draco_read_nand_geometry();
 249         if (ret != 0)
 250                 return ret;
 251
 252         nand_curr_device = 0;
 253         omap_nand_switch_ecc(1, ecc_type);
 254 #ifdef CONFIG_FACTORYSET
 255         /* Set ASN in environment*/
 256         if (factory_dat.asn[0] != 0) {
 257                 setenv("dtb_name", (char *)factory_dat.asn);
 258         } else {
 259                 /* dtb suffix gets added in load script */
 260                 setenv("dtb_name", "am335x-draco");
 261         }
 262 #else
 263         setenv("dtb_name", "am335x-draco");
 264 #endif
 265
 266         return 0;
 267 }
 268 #endif
 269
 270 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 271         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 272 static void cpsw_control(int enabled)
 273 {
 274         /* VTP can be added here */
 275
 276         return;
 277 }
 278
 279 static struct cpsw_slave_data cpsw_slaves[] = {
 280         {
 281                 .slave_reg_ofs  = 0x208,
 282                 .sliver_reg_ofs = 0xd80,
 283                 .phy_addr       = 0,
 284                 .phy_if         = PHY_INTERFACE_MODE_MII,
 285         },
 286 };
 287
 288 static struct cpsw_platform_data cpsw_data = {
 289         .mdio_base              = CPSW_MDIO_BASE,
 290         .cpsw_base              = CPSW_BASE,
 291         .mdio_div               = 0xff,
 292         .channels               = 4,
 293         .cpdma_reg_ofs          = 0x800,
 294         .slaves                 = 1,
 295         .slave_data             = cpsw_slaves,
 296         .ale_reg_ofs            = 0xd00,
 297         .ale_entries            = 1024,
 298         .host_port_reg_ofs      = 0x108,
 299         .hw_stats_reg_ofs       = 0x900,
 300         .bd_ram_ofs             = 0x2000,
 301         .mac_control            = (1 << 5),
 302         .control                = cpsw_control,
 303         .host_port_num          = 0,
 304         .version                = CPSW_CTRL_VERSION_2,
 305 };
 306
 307 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 308         (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
 309 int board_eth_init(bd_t *bis)
 310 {
 311         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 312         int n = 0;
 313         int rv;
 314
 315         factoryset_setenv();
 316
 317         /* Set rgmii mode and enable rmii clock to be sourced from chip */
 318         writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
 319
 320         rv = cpsw_register(&cpsw_data);
 321         if (rv < 0)
 322                 printf("Error %d registering CPSW switch\n", rv);
 323         else
 324                 n += rv;
 325         return n;
 326 }
 327
 328 static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
 329                            char *const argv[])
 330 {
 331         /* Reset SMSC LAN9303 switch for default configuration */
 332         gpio_request(GPIO_LAN9303_NRST, "nRST");
 333         gpio_direction_output(GPIO_LAN9303_NRST, 0);
 334         /* assert active low reset for 200us */
 335         udelay(200);
 336         gpio_set_value(GPIO_LAN9303_NRST, 1);
 337
 338         return 0;
 339 };
 340
 341 U_BOOT_CMD(
 342         switch_rst, CONFIG_SYS_MAXARGS, 1,      do_switch_reset,
 343         "Reset LAN9303 switch via its reset pin",
 344         ""
 345 );
 346 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 347 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 348
 349 #include "../common/board.c"