4 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/ic/sc520.h>
30 #include <asm/ic/pci.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #undef SC520_CDP_DEBUG
36 #ifdef SC520_CDP_DEBUG
37 #define PRINTF(fmt,args...) printf (fmt ,##args)
39 #define PRINTF(fmt,args...)
42 static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
44 /* a configurable lists of irqs to steal
45 * when we need one (a board with more pci interrupt pins
46 * would use a larger table */
47 static int irq_list[] = {
48 CONFIG_SYS_FIRST_PCI_IRQ,
49 CONFIG_SYS_SECOND_PCI_IRQ,
50 CONFIG_SYS_THIRD_PCI_IRQ,
51 CONFIG_SYS_FORTH_PCI_IRQ
53 static int next_irq_index=0;
58 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
61 pin-=1; /* pci config space use 1-based numbering */
63 return; /* device use no irq */
67 /* map device number + pin to a pin on the sc520 */
68 switch (PCI_DEV(dev)) {
89 pin&=3; /* wrap around */
91 if (sc520_pci_ints[pin] == -1) {
92 /* re-route one interrupt for us */
93 if (next_irq_index > 3) {
96 if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
103 if (-1 != sc520_pci_ints[pin]) {
104 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
105 sc520_pci_ints[pin]);
107 PRINTF("fixup_irq: device %d pin %c irq %d\n",
108 PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
111 static struct pci_controller sc520_cdp_hose = {
112 fixup_irq: pci_sc520_cdp_fixup_irq,
115 void pci_init_board(void)
117 pci_sc520_init(&sc520_cdp_hose);
121 * This function should map a chunk of size bytes
122 * of the system address space to the ISA bus
124 * The function will return the memory address
125 * as seen by the host (which may very will be the
126 * same as the bus address)
128 u32 isa_map_rom(u32 bus_addr, int size)
132 PRINTF("isa_map_rom asked to map %d bytes at %x\n",
143 par |= (bus_addr>>12);
146 PRINTF ("setting PAR11 to %x\n", par);
148 /* Map rom 0x10000 with PAR1 */
149 sc520_mmcr->par[11] = par;
155 * this function removed any mapping created
156 * with pci_get_rom_window()
158 void isa_unmap_rom(u32 addr)
160 PRINTF("isa_unmap_rom asked to unmap %x", addr);
161 if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) {
162 sc520_mmcr->par[11] = 0;
166 PRINTF(" not ours\n");
169 #define PCI_ROM_TEMP_SPACE 0x10000
171 * This function should map a chunk of size bytes
172 * of the system address space to the PCI bus,
173 * suitable to map PCI ROMS (bus address < 16M)
174 * the function will return the host memory address
175 * which should be converted into a bus address
176 * before used to configure the PCI rom address
179 u32 pci_get_rom_window(struct pci_controller *hose, int size)
191 par |= (PCI_ROM_TEMP_SPACE>>16);
194 PRINTF ("setting PAR1 to %x\n", par);
196 /* Map rom 0x10000 with PAR1 */
197 sc520_mmcr->par[1] = par;
199 return PCI_ROM_TEMP_SPACE;
203 * this function removed any mapping created
204 * with pci_get_rom_window()
206 void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
208 PRINTF("pci_remove_rom_window: %x", addr);
209 if (addr == PCI_ROM_TEMP_SPACE) {
210 sc520_mmcr->par[1] = 0;
214 PRINTF(" not ours\n");
219 * This function is called in order to provide acces to the
220 * legacy video I/O ports on the PCI bus.
221 * After this function accesses to I/O ports 0x3b0-0x3bb and
222 * 0x3c0-0x3df shuld result in transactions on the PCI bus.
225 int pci_enable_legacy_video_ports(struct pci_controller *hose)
227 /* Map video memory to 0xa0000*/
228 sc520_mmcr->par[0] = 0x7200400a;
230 /* forward all I/O accesses to PCI */
231 sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI;
234 /* so we map away all io ports to pci (only way to access pci io
235 * below 0x400. But then we have to map back the portions that we dont
236 * use so that the generate cycles on the GPIO bus where the sio and
237 * ISA slots are connected, this requre the use of several PAR registers
240 /* bring 0x100 - 0x1ef back to ISA using PAR5 */
241 sc520_mmcr->par[5] = 0x30ef0100;
243 /* IDE use 1f0-1f7 */
245 /* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
246 sc520_mmcr->par[6] = 0x30ff01f8;
248 /* com2 use 2f8-2ff */
250 /* bring 0x300 - 0x3af back to ISA using PAR7 */
251 sc520_mmcr->par[7] = 0x30af0300;
253 /* vga use 3b0-3bb */
255 /* bring 0x3bc - 0x3bf back to ISA using PAR8 */
256 sc520_mmcr->par[8] = 0x300303bc;
258 /* vga use 3c0-3df */
260 /* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
261 sc520_mmcr->par[9] = 0x301503e0;
265 /* bring 0x3f7 back to ISA using PAR10 */
266 sc520_mmcr->par[10] = 0x300003f7;
268 /* com1 use 3f8-3ff */