board/sbc8641d/ddr.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <i2c.h>
  11
  12 #include <asm/fsl_ddr_sdram.h>
  13
  14 static void
  15 get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
  16 {
  17         i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
  18 }
  19
  20 unsigned int fsl_ddr_get_mem_data_rate(void)
  21 {
  22         return get_bus_freq(0);
  23 }
  24
  25 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
  26                       unsigned int ctrl_num)
  27 {
  28         unsigned int i;
  29         unsigned int i2c_address = 0;
  30
  31         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
  32                 if (ctrl_num == 0 && i == 0) {
  33                         i2c_address = SPD_EEPROM_ADDRESS1;
  34                 }
  35                 if (ctrl_num == 0 && i == 1) {
  36                         i2c_address = SPD_EEPROM_ADDRESS2;
  37                 }
  38                 if (ctrl_num == 1 && i == 0) {
  39                         i2c_address = SPD_EEPROM_ADDRESS3;
  40                 }
  41                 if (ctrl_num == 1 && i == 1) {
  42                         i2c_address = SPD_EEPROM_ADDRESS4;
  43                 }
  44                 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
  45         }
  46 }
  47
  48 void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
  49 {
  50         /*
  51          * Factors to consider for clock adjust:
  52          *      - number of chips on bus
  53          *      - position of slot
  54          *      - DDR1 vs. DDR2?
  55          *      - ???
  56          *
  57          * This needs to be determined on a board-by-board basis.
  58          *      0110    3/4 cycle late
  59          *      0111    7/8 cycle late
  60          */
  61         popts->clk_adjust = 7;
  62
  63         /*
  64          * Factors to consider for CPO:
  65          *      - frequency
  66          *      - ddr1 vs. ddr2
  67          */
  68         popts->cpo_override = 10;
  69
  70         /*
  71          * Factors to consider for write data delay:
  72          *      - number of DIMMs
  73          *
  74          * 1 = 1/4 clock delay
  75          * 2 = 1/2 clock delay
  76          * 3 = 3/4 clock delay
  77          * 4 = 1   clock delay
  78          * 5 = 5/4 clock delay
  79          * 6 = 3/2 clock delay
  80          */
  81         popts->write_data_delay = 3;
  82
  83         /*
  84          * Factors to consider for half-strength driver enable:
  85          *      - number of DIMMs installed
  86          */
  87         popts->half_strength_driver_enable = 0;
  88 }