board/sbc8548/tlb.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/mmu.h>
  28
  29 struct fsl_e_tlb_entry tlb_table[] = {
  30         /* TLB 0 - for temp stack in cache */
  31         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  32                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  33                       0, 0, BOOKE_PAGESZ_4K, 0),
  34         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  35                       CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  36                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  37                       0, 0, BOOKE_PAGESZ_4K, 0),
  38         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  39                       CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  40                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  41                       0, 0, BOOKE_PAGESZ_4K, 0),
  42         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  43                       CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  44                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  45                       0, 0, BOOKE_PAGESZ_4K, 0),
  46
  47         /*
  48          * TLB 0:       64M     Non-cacheable, guarded
  49          * 0xfc000000   56M     8MB -> 64MB of user flash
  50          * 0xff800000   8M      boot FLASH
  51          * Out of reset this entry is only 4K.
  52          */
  53         SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x800000,
  54                       CONFIG_SYS_ALT_FLASH + 0x800000,
  55                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  56                       0, 0, BOOKE_PAGESZ_64M, 1),
  57
  58         /*
  59          * TLB 1:       1G      Non-cacheable, guarded
  60          * 0x80000000   512M    PCI1 MEM
  61          * 0xa0000000   512M    PCIe MEM
  62          */
  63         SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
  64                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  65                       0, 1, BOOKE_PAGESZ_1G, 1),
  66
  67         /*
  68          * TLB 2:       256M Cacheable, non-guarded
  69          * 0x0          256M DDR SDRAM
  70          */
  71 #if !defined(CONFIG_SPD_EEPROM)
  72         SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  73                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  74                       0, 2, BOOKE_PAGESZ_256M, 1),
  75 #endif
  76
  77         /*
  78          * TLB 3:       64M     Non-cacheable, guarded
  79          * 0xe0000000   1M      CCSRBAR
  80          * 0xe2000000   8M      PCI1 IO
  81          * 0xe2800000   8M      PCIe IO
  82          */
  83         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  84                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  85                       0, 3, BOOKE_PAGESZ_64M, 1),
  86
  87         /*
  88          * TLB 4:       64M     Cacheable, non-guarded
  89          * 0xf0000000   64M     LBC SDRAM First half
  90          */
  91         SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
  92                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  93                       0, 4, BOOKE_PAGESZ_64M, 1),
  94
  95         /*
  96          * TLB 5:       64M     Cacheable, non-guarded
  97          * 0xf4000000   64M     LBC SDRAM Second half
  98          */
  99         SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
 100                       CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
 101                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
 102                       0, 5, BOOKE_PAGESZ_64M, 1),
 103
 104         /*
 105          * TLB 6:       16M     Cacheable, non-guarded
 106          * 0xf8000000   1M      7-segment LED display
 107          * 0xf8100000   1M      User switches
 108          * 0xf8300000   1M      Board revision
 109          * 0xf8b00000   1M      EEPROM
 110          */
 111         SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
 112                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 113                       0, 6, BOOKE_PAGESZ_16M, 1),
 114
 115         /*
 116          * TLB 7:       4M      Non-cacheable, guarded
 117          * 0xfb800000   4M      1st 4MB block of 64MB user FLASH
 118          */
 119         SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
 120                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 121                       0, 7, BOOKE_PAGESZ_4M, 1),
 122
 123         /*
 124          * TLB 8:       4M      Non-cacheable, guarded
 125          * 0xfbc00000   4M      2nd 4MB block of 64MB user FLASH
 126          */
 127         SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
 128                       CONFIG_SYS_ALT_FLASH + 0x400000,
 129                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 130                       0, 8, BOOKE_PAGESZ_4M, 1),
 131
 132 };
 133
 134 int num_tlb_entries = ARRAY_SIZE(tlb_table);