2 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
4 * Copyright 2007 Embedded Specialties, Inc.
6 * Copyright 2004, 2007 Freescale Semiconductor.
8 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
32 #include <asm/immap_85xx.h>
33 #include <asm/fsl_pci.h>
34 #include <asm/fsl_ddr_sdram.h>
35 #include <asm/fsl_serdes.h>
36 #include <spd_sdram.h>
41 #include <fdt_support.h>
43 DECLARE_GLOBAL_DATA_PTR;
45 void local_bus_init(void);
47 int board_early_init_f (void)
54 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
55 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
57 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
61 * Initialize local bus.
65 out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
66 out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
71 * Initialize Local Bus
76 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
77 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
83 get_sys_info(&sysinfo);
84 clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
85 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
87 out_be32(&gur->lbiuiplldcr1, 0x00078080);
89 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
90 } else if (clkdiv == 8) {
91 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
92 } else if (clkdiv == 4) {
93 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
96 setbits_be32(&lbc->lcrr, 0x00030000);
98 asm("sync;isync;msync");
100 out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
101 out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
105 * Initialize SDRAM memory on the Local Bus.
110 #if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
113 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
114 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
119 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
122 * Setup SDRAM Base and Option Registers
124 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
125 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
126 set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
127 set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
129 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
132 out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
133 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
137 * MPC8548 uses "new" 15-16 style addressing.
139 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
140 lsdmr_common |= LSDMR_BSMA1516;
143 * Issue PRECHARGE ALL command.
145 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL);
148 ppcDcbf((unsigned long) sdram_addr);
152 * Issue 8 AUTO REFRESH commands.
154 for (idx = 0; idx < 8; idx++) {
155 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH);
158 ppcDcbf((unsigned long) sdram_addr);
163 * Issue 8 MODE-set command.
165 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW);
168 ppcDcbf((unsigned long) sdram_addr);
172 * Issue NORMAL OP command.
174 out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL);
177 ppcDcbf((unsigned long) sdram_addr);
178 udelay(200); /* Overkill. Must wait > 200 bus cycles */
180 #endif /* enable SDRAM init */
183 #if defined(CONFIG_SYS_DRAM_TEST)
187 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
188 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
191 printf("Testing DRAM from 0x%08x to 0x%08x\n",
192 CONFIG_SYS_MEMTEST_START,
193 CONFIG_SYS_MEMTEST_END);
195 printf("DRAM test phase 1:\n");
196 for (p = pstart; p < pend; p++)
199 for (p = pstart; p < pend; p++) {
200 if (*p != 0xaaaaaaaa) {
201 printf ("DRAM test fails at: %08x\n", (uint) p);
206 printf("DRAM test phase 2:\n");
207 for (p = pstart; p < pend; p++)
210 for (p = pstart; p < pend; p++) {
211 if (*p != 0x55555555) {
212 printf ("DRAM test fails at: %08x\n", (uint) p);
217 printf("DRAM test passed.\n");
222 #if !defined(CONFIG_SPD_EEPROM)
223 #define CONFIG_SYS_DDR_CONTROL 0xc300c000
224 /*************************************************************************
225 * fixed_sdram init -- doesn't use serial presence detect.
226 * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
227 ************************************************************************/
228 phys_size_t fixed_sdram(void)
230 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
232 out_be32(&ddr->cs0_bnds, 0x0000007f);
233 out_be32(&ddr->cs1_bnds, 0x008000ff);
234 out_be32(&ddr->cs2_bnds, 0x00000000);
235 out_be32(&ddr->cs3_bnds, 0x00000000);
236 out_be32(&ddr->cs0_config, 0x80010101);
237 out_be32(&ddr->cs1_config, 0x80010101);
238 out_be32(&ddr->cs2_config, 0x00000000);
239 out_be32(&ddr->cs3_config, 0x00000000);
240 out_be32(&ddr->timing_cfg_3, 0x00000000);
241 out_be32(&ddr->timing_cfg_0, 0x00220802);
242 out_be32(&ddr->timing_cfg_1, 0x38377322);
243 out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
244 out_be32(&ddr->sdram_cfg, 0x4300C000);
245 out_be32(&ddr->sdram_cfg_2, 0x24401000);
246 out_be32(&ddr->sdram_mode, 0x23C00542);
247 out_be32(&ddr->sdram_mode_2, 0x00000000);
248 out_be32(&ddr->sdram_interval, 0x05080100);
249 out_be32(&ddr->sdram_md_cntl, 0x00000000);
250 out_be32(&ddr->sdram_data_init, 0x00000000);
251 out_be32(&ddr->sdram_clk_cntl, 0x03800000);
252 asm("sync;isync;msync");
255 #if defined (CONFIG_DDR_ECC)
256 /* Enable ECC checking */
257 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
259 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
262 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
267 static struct pci_controller pci1_hose;
268 #endif /* CONFIG_PCI1 */
271 static struct pci_controller pcie1_hose;
272 #endif /* CONFIG_PCIE1 */
279 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
280 struct fsl_pci_info pci_info[2];
281 u32 devdisr, pordevsr, porpllsr, io_sel;
282 int first_free_busno = 0;
289 devdisr = in_be32(&gur->devdisr);
290 pordevsr = in_be32(&gur->pordevsr);
291 porpllsr = in_be32(&gur->porpllsr);
292 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
294 debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
297 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
298 uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
299 uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
300 uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
301 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
303 printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
305 (pci_speed == 33000000) ? "33" :
306 (pci_speed == 66000000) ? "66" : "unknown",
307 pci_clk_sel ? "sync" : "async",
308 pci_arb ? "arbiter" : "external-arbiter");
310 SET_STD_PCI_INFO(pci_info[num], 1);
311 first_free_busno = fsl_pci_init_port(&pci_info[num++],
312 &pci1_hose, first_free_busno);
314 printf("PCI: disabled\n");
319 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
322 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
325 pcie_configured = is_serdes_configured(PCIE1);
327 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
328 SET_STD_PCIE_INFO(pci_info[num], 1);
329 printf("PCIE: base address %lx\n", pci_info[num].regs);
330 first_free_busno = fsl_pci_init_port(&pci_info[num++],
331 &pcie1_hose, first_free_busno);
333 printf("PCIE: disabled\n");
338 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
343 int board_eth_init(bd_t *bis)
345 tsec_standard_init(bis);
347 return 0; /* otherwise cpu_eth_init gets run */
350 int last_stage_init(void)
355 #if defined(CONFIG_OF_BOARD_SETUP)
356 void ft_board_setup(void *blob, bd_t *bd)
358 ft_cpu_setup(blob, bd);
360 #ifdef CONFIG_FSL_PCI_INIT