2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
7 * Modified for the Samsung SMDK2410 by
9 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
11 * Modified for the friendly-arm SBC-2410X by
13 * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
40 * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
43 #define BWSCON 0x48000000
52 #define B1_BWSCON (DW16)
53 #define B2_BWSCON (DW16)
54 #define B3_BWSCON (DW16 + WAIT + UBLB)
55 #define B4_BWSCON (DW16)
56 #define B5_BWSCON (DW16)
57 #define B6_BWSCON (DW32)
58 #define B7_BWSCON (DW32)
108 #define B6_MT 0x3 /* SDRAM */
110 #define B6_SCAN 0x1 /* 9bit */
112 #define B7_MT 0x3 /* SDRAM */
113 #define B7_Trcd 0x1 /* 3clk */
114 #define B7_SCAN 0x1 /* 9bit */
116 /* REFRESH parameter */
117 #define REFEN 0x1 /* Refresh enable */
118 #define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
119 #define Trp 0x0 /* 2clk */
120 #define Trc 0x3 /* 7clk */
121 #define Tchr 0x2 /* 3clk */
122 #define REFCNT 0x0459
123 /**************************************/
130 /* memory control configuration */
131 /* make r0 relative the current location so that it */
132 /* reads SMRDATA out of FLASH rather than memory ! */
136 ldr r1, =BWSCON /* Bus Width Status Controller */
144 /* everything is fine now */
148 /* the literal pools origin */
151 .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
152 .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
153 .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
154 .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
155 .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
156 .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
157 .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
158 .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
159 .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
160 .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)