3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
8 /*-----------------------------------------------------------------------
9 * Timer value for timer 2, ICLK = 10
11 * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1))
12 * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
14 * SPEED_FCOUNT2 timer 2 counting frequency
16 * SPEED_TMR2_PS prescaler
18 #define SPEED_TMR2_PS (250 - 1) /* divide by 250 */
20 /*-----------------------------------------------------------------------
23 * PIT_TIME = SPEED_PITC / PITRTCLK
26 #define SPEED_PITC (82 << 16) /* start counting from 82 */
29 * The new value for PTA is calculated from
31 * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
33 * gclk CPU clock (not bus clock !)
34 * Trefresh Refresh cycle * 4 (four word bursts used)
35 * DFBRG For normal mode (no clock reduction) always 0
36 * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
37 * NCS Number of SDRAM banks (chip selects) on this UPM.