board/sandburst/karef/karef.c

   1 /*
   2  *  Copyright (C) 2005 Sandburst Corporation
   3  *  Travis B. Sawyer
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <config.h>
  25 #include <common.h>
  26 #include <command.h>
  27 #include "karef.h"
  28 #include "karef_version.h"
  29 #include <asm/processor.h>
  30 #include <asm/io.h>
  31 #include <spd_sdram.h>
  32 #include <i2c.h>
  33 #include "../common/sb_common.h"
  34 #include "../common/ppc440gx_i2c.h"
  35
  36
  37
  38 void fpga_init (void);
  39
  40 KAREF_BOARD_ID_ST board_id_as[] =
  41 {
  42         {"Undefined"},                       /* Not specified */
  43         {"Kamino Reference Design"},
  44         {"Reserved"},                        /* Reserved for future use */
  45         {"Reserved"},                        /* Reserved for future use */
  46 };
  47
  48 KAREF_BOARD_ID_ST ofem_board_id_as[] =
  49 {
  50         {"Undefined"},
  51         {"1x10 + 10x2"},
  52         {"Reserved"},
  53         {"Reserved"},
  54 };
  55
  56
  57 /*************************************************************************
  58  *  board_early_init_f
  59  *
  60  *  Setup chip selects, initialize the Opto-FPGA, initialize
  61  *  interrupt polarity and triggers.
  62  *
  63  ************************************************************************/
  64 int board_early_init_f (void)
  65 {
  66         ppc440_gpio_regs_t *gpio_regs;
  67
  68         /* Enable GPIO interrupts */
  69         mtsdr(sdr_pfc0, 0x00103E00);
  70
  71         /* Setup access for LEDs, and system topology info */
  72         gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
  73         gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
  74         gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
  75
  76         /* Turn on all the leds for now */
  77         gpio_regs->out = SBCOMMON_GPIO_LEDS;
  78
  79         /*--------------------------------------------------------------------+
  80           | Initialize EBC CONFIG
  81           +-------------------------------------------------------------------*/
  82         mtebc(xbcfg,
  83               EBC_CFG_LE_UNLOCK    | EBC_CFG_PTD_ENABLE |
  84               EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
  85               EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
  86               EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
  87               EBC_CFG_PR_32);
  88
  89         /*--------------------------------------------------------------------+
  90           | 1/2 MB FLASH. Initialize bank 0 with default values.
  91           +-------------------------------------------------------------------*/
  92         mtebc(pb0ap,
  93               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
  94               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
  95               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
  96               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
  97               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
  98               EBC_BXAP_PEN_DISABLED);
  99
 100         mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
 101               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
 102         /*--------------------------------------------------------------------+
 103           | 8KB NVRAM/RTC. Initialize bank 1 with default values.
 104           +-------------------------------------------------------------------*/
 105         mtebc(pb1ap,
 106               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
 107               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 108               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 109               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
 110               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 111               EBC_BXAP_PEN_DISABLED);
 112
 113         mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
 114               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
 115
 116         /*--------------------------------------------------------------------+
 117           | Compact Flash, uses 2 Chip Selects (2 & 6)
 118           +-------------------------------------------------------------------*/
 119         mtebc(pb2ap,
 120               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 121               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 122               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 123               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 124               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 125               EBC_BXAP_PEN_DISABLED);
 126
 127         mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
 128               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 129
 130         /*--------------------------------------------------------------------+
 131           | KaRef Scan FPGA. Initialize bank 3 with default values.
 132           +-------------------------------------------------------------------*/
 133         mtebc(pb5ap,
 134               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 135               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 136               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 137               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 138               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 139
 140         mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
 141               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 142
 143         /*--------------------------------------------------------------------+
 144           | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
 145           | Initialize bank 4 with default values.
 146           +-------------------------------------------------------------------*/
 147         mtebc(pb4ap,
 148               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 149               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 150               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 151               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 152               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 153
 154         mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
 155               EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 156
 157         /*--------------------------------------------------------------------+
 158           | OFEM FPGA  Initialize bank 5 with default values.
 159           +-------------------------------------------------------------------*/
 160         mtebc(pb3ap,
 161               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 162               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 163               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 164               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 165               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 166
 167
 168         mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) |
 169               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 170
 171
 172         /*--------------------------------------------------------------------+
 173           | Compact Flash, uses 2 Chip Selects (2 & 6)
 174           +-------------------------------------------------------------------*/
 175         mtebc(pb6ap,
 176               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 177               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 178               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 179               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 180               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 181               EBC_BXAP_PEN_DISABLED);
 182
 183         mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
 184               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 185
 186         /*--------------------------------------------------------------------+
 187           | BME-32. Initialize bank 7 with default values.
 188           +-------------------------------------------------------------------*/
 189         mtebc(pb7ap,
 190               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 191               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 192               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 193               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 194               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 195
 196         mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
 197               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 198
 199
 200         /*--------------------------------------------------------------------+
 201          * Setup the interrupt controller polarities, triggers, etc.
 202          +-------------------------------------------------------------------*/
 203         mtdcr (uic0sr, 0xffffffff);     /* clear all */
 204         mtdcr (uic0er, 0x00000000);     /* disable all */
 205         mtdcr (uic0cr, 0x00000000);     /* all non- critical */
 206         mtdcr (uic0pr, 0xfffffe03);     /* polarity */
 207         mtdcr (uic0tr, 0x01c00000);     /* trigger edge vs level */
 208         mtdcr (uic0vr, 0x00000001);     /* int31 highest, base=0x000 */
 209         mtdcr (uic0sr, 0xffffffff);     /* clear all */
 210
 211         mtdcr (uic1sr, 0xffffffff);     /* clear all */
 212         mtdcr (uic1er, 0x00000000);     /* disable all */
 213         mtdcr (uic1cr, 0x00000000);     /* all non-critical */
 214         mtdcr (uic1pr, 0xffffc8ff);     /* polarity */
 215         mtdcr (uic1tr, 0x00ff0000);     /* trigger edge vs level */
 216         mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
 217         mtdcr (uic1sr, 0xffffffff);     /* clear all */
 218
 219         mtdcr (uic2sr, 0xffffffff);     /* clear all */
 220         mtdcr (uic2er, 0x00000000);     /* disable all */
 221         mtdcr (uic2cr, 0x00000000);     /* all non-critical */
 222         mtdcr (uic2pr, 0xffff83ff);     /* polarity */
 223         mtdcr (uic2tr, 0x00ff8c0f);     /* trigger edge vs level */
 224         mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
 225         mtdcr (uic2sr, 0xffffffff);     /* clear all */
 226
 227         mtdcr (uicb0sr, 0xfc000000);    /* clear all */
 228         mtdcr (uicb0er, 0x00000000);    /* disable all */
 229         mtdcr (uicb0cr, 0x00000000);    /* all non-critical */
 230         mtdcr (uicb0pr, 0xfc000000);
 231         mtdcr (uicb0tr, 0x00000000);
 232         mtdcr (uicb0vr, 0x00000001);
 233
 234         fpga_init();
 235
 236         return 0;
 237 }
 238
 239
 240 /*************************************************************************
 241  *  checkboard
 242  *
 243  *  Dump pertinent info to the console
 244  *
 245  ************************************************************************/
 246 int checkboard (void)
 247 {
 248         sys_info_t sysinfo;
 249         unsigned char brd_rev, brd_id;
 250         unsigned short sernum;
 251         unsigned char scan_rev, scan_id, ofem_rev, ofem_id;
 252         unsigned char ofem_brd_rev, ofem_brd_id;
 253         KAREF_FPGA_REGS_ST *karef_ps;
 254         OFEM_FPGA_REGS_ST *ofem_ps;
 255
 256         karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
 257         ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
 258
 259         scan_id = (unsigned char)((karef_ps->revision_ul &
 260                                    SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
 261                                   >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
 262
 263         scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
 264                                    >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
 265
 266         brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
 267                                   >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
 268
 269         brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
 270                                  >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
 271
 272         ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
 273                                       >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
 274
 275         ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
 276                                        >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
 277
 278         if (0xF != ofem_brd_id) {
 279                 ofem_id = (unsigned char)((ofem_ps->revision_ul &
 280                                            SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
 281                                           >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
 282
 283                 ofem_rev = (unsigned char)((ofem_ps->revision_ul &
 284                                             SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
 285                                            >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
 286         }
 287
 288         get_sys_info (&sysinfo);
 289
 290         sernum = sbcommon_get_serial_number();
 291
 292         printf ("Board: Sandburst Corporation Kamino Reference Design "
 293                 "Serial Number: %d\n", sernum);
 294         printf ("%s\n", KAREF_U_BOOT_REL_STR);
 295
 296         printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
 297         if (sbcommon_get_master()) {
 298                 printf("Slot 0 - Master\nSlave board");
 299                 if (sbcommon_secondary_present())
 300                         printf(" present\n");
 301                 else
 302                         printf(" not detected\n");
 303         } else {
 304                 printf("Slot 1 - Slave\n\n");
 305         }
 306
 307         printf ("ScanFPGA ID:\t0x%02X\tRev:  0x%02X\n", scan_id, scan_rev);
 308         printf ("Board Rev:\t0x%02X\tID:   0x%02X\n", brd_rev, brd_id);
 309         if(0xF != ofem_brd_id) {
 310                 printf("OFemFPGA ID:\t0x%02X\tRev:  0x%02X\n", ofem_id, ofem_rev);
 311                 printf("OFEM Board Rev:\t0x%02X\tID:   0x%02X\n", ofem_brd_id, ofem_brd_rev);
 312         }
 313
 314         printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
 315         printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
 316         printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
 317         printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
 318         printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
 319
 320         /* Fix the ack in the bme 32 */
 321         udelay(5000);
 322         out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
 323         asm("eieio");
 324
 325
 326         return (0);
 327 }
 328
 329
 330 /*************************************************************************
 331  *  misc_init_f
 332  *
 333  *  Initialize I2C bus one to gain access to the fans
 334  *
 335  ************************************************************************/
 336 int misc_init_f (void)
 337 {
 338         /* Turn on i2c bus 1 */
 339         puts ("I2C1:  ");
 340         i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
 341         puts ("ready\n");
 342
 343         /* Turn on fans 3 & 4 */
 344         sbcommon_fans();
 345
 346         return (0);
 347 }
 348 /*************************************************************************
 349  *  misc_init_r
 350  *
 351  *  Do nothing.
 352  *
 353  ************************************************************************/
 354 int misc_init_r (void)
 355 {
 356         unsigned short sernum;
 357         char envstr[255];
 358         KAREF_FPGA_REGS_ST *karef_ps;
 359         OFEM_FPGA_REGS_ST *ofem_ps;
 360         unsigned char ofem_id;
 361
 362         if(NULL != getenv("secondserial")) {
 363                 puts("secondserial is set, switching to second serial port\n");
 364                 setenv("stderr", "serial1");
 365                 setenv("stdout", "serial1");
 366                 setenv("stdin", "serial1");
 367         }
 368
 369         setenv("ubrelver", KAREF_U_BOOT_REL_STR);
 370
 371         memset(envstr, 0, 255);
 372         sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
 373         setenv("bldstr", envstr);
 374         saveenv();
 375
 376         if( getenv("autorecover")) {
 377                 setenv("autorecover", NULL);
 378                 saveenv();
 379                 sernum = sbcommon_get_serial_number();
 380
 381                 printf("\nSetting up environment for automatic filesystem recovery\n");
 382                 /*
 383                  * Setup default bootargs
 384                  */
 385                 memset(envstr, 0, 255);
 386
 387                 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 388                         "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
 389                         sernum, sernum);
 390                 setenv("bootargs", envstr);
 391
 392                 /*
 393                  * Setup Default boot command
 394                  */
 395                 setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
 396                        "fatload ide 0 8100000 pramdisk;"
 397                        "bootm 8000000 8100000");
 398
 399                 printf("Done.  Please type allow the system to continue to boot\n");
 400         }
 401
 402         if( getenv("fakeled")) {
 403                 karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
 404                 ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
 405                 ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
 406                 karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
 407                 setenv("bootdelay", "-1");
 408                 saveenv();
 409                 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
 410         }
 411
 412
 413
 414
 415         return (0);
 416 }
 417
 418
 419
 420
 421 /*************************************************************************
 422  *  ide_set_reset
 423  *
 424  *
 425  *
 426  ************************************************************************/
 427 #ifdef CONFIG_IDE_RESET
 428 void ide_set_reset(int on)
 429 {
 430         KAREF_FPGA_REGS_ST *karef_ps;
 431         /* TODO: ide reset */
 432         karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
 433
 434         if (on) {
 435                 karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
 436         } else {
 437                 karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
 438         }
 439 }
 440 #endif /* CONFIG_IDE_RESET */
 441
 442 /*************************************************************************
 443  *  fpga_init
 444  *
 445  *
 446  *
 447  ************************************************************************/
 448 void fpga_init(void)
 449 {
 450         KAREF_FPGA_REGS_ST *karef_ps;
 451         OFEM_FPGA_REGS_ST *ofem_ps;
 452         unsigned char ofem_id;
 453         unsigned long tmp;
 454
 455         /* Ensure we have power all around */
 456         udelay(500);
 457
 458         karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
 459         tmp =
 460                 SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
 461                 SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
 462                 SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
 463                 SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
 464                 SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
 465                 SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
 466                 SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
 467                 SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
 468                 SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
 469
 470         karef_ps->reset_ul = tmp;
 471
 472         /*
 473          * Wait a bit to allow the ofem fpga to get its brains
 474          */
 475         udelay(5000);
 476
 477         /*
 478          * Check to see if the ofem is there
 479          */
 480         ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
 481                                   >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
 482         if(0xF != ofem_id) {
 483                 tmp =
 484                         SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
 485                         SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
 486                         SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
 487
 488                 ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
 489                 ofem_ps->reset_ul = tmp;
 490
 491                 ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
 492         }
 493
 494         karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
 495
 496         asm("eieio");
 497
 498         return;
 499 }
 500
 501
 502
 503 int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 504 {
 505         unsigned short sernum;
 506         char envstr[255];
 507
 508         sernum = sbcommon_get_serial_number();
 509
 510         memset(envstr, 0, 255);
 511         /*
 512          * Setup our ip address
 513          */
 514         sprintf(envstr, "10.100.70.%d", sernum);
 515
 516         setenv("ipaddr", envstr);
 517         /*
 518          * Setup the host ip address
 519          */
 520         setenv("serverip", "10.100.17.10");
 521
 522         /*
 523          * Setup default bootargs
 524          */
 525         memset(envstr, 0, 255);
 526
 527         sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
 528                 "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
 529                 "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
 530                 "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
 531                 sernum, sernum, sernum);
 532
 533         setenv("bootargs_nfs", envstr);
 534         setenv("bootargs", envstr);
 535
 536         /*
 537          * Setup CF bootargs
 538          */
 539         memset(envstr, 0, 255);
 540
 541         sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
 542                 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
 543                 sernum, sernum);
 544
 545         setenv("bootargs_cf", envstr);
 546
 547         /*
 548          * Setup Default boot command
 549          */
 550         setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
 551         setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
 552
 553         /*
 554          * Setup compact flash boot command
 555          */
 556         setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
 557
 558         saveenv();
 559
 560         return(1);
 561 }
 562
 563
 564 int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 565 {
 566         unsigned short sernum;
 567         char envstr[255];
 568
 569         sernum = sbcommon_get_serial_number();
 570
 571         printf("\nSetting up environment for filesystem recovery\n");
 572         /*
 573          * Setup default bootargs
 574          */
 575         memset(envstr, 0, 255);
 576
 577         sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 578                 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
 579                 sernum, sernum);
 580         setenv("bootargs", envstr);
 581
 582         /*
 583          * Setup Default boot command
 584          */
 585
 586         setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
 587                "fatload ide 0 8100000 pramdisk;"
 588                "bootm 8000000 8100000");
 589
 590         printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
 591                " please type fsrecover.sh<cr>\n");
 592
 593         return(1);
 594 }
 595
 596
 597
 598
 599
 600
 601
 602 U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
 603            "kasetup - Set environment to factory defaults\n", NULL);
 604
 605 U_BOOT_CMD(karecover, 1, 1, karefRecover,
 606            "karecover - Set environment to allow for fs recovery\n", NULL);
 607