2 * Copyright (C) 2005 Sandburst Corporation
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include "karef_version.h"
29 #include <timestamp.h>
30 #include <asm/processor.h>
32 #include <spd_sdram.h>
34 #include "../common/sb_common.h"
35 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
36 defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
40 void fpga_init (void);
42 KAREF_BOARD_ID_ST board_id_as[] =
44 {"Undefined"}, /* Not specified */
45 {"Kamino Reference Design"},
46 {"Reserved"}, /* Reserved for future use */
47 {"Reserved"}, /* Reserved for future use */
50 KAREF_BOARD_ID_ST ofem_board_id_as[] =
58 /*************************************************************************
61 * Setup chip selects, initialize the Opto-FPGA, initialize
62 * interrupt polarity and triggers.
63 ************************************************************************/
64 int board_early_init_f (void)
66 ppc440_gpio_regs_t *gpio_regs;
68 /* Enable GPIO interrupts */
69 mtsdr(SDR0_PFC0, 0x00103E00);
71 /* Setup access for LEDs, and system topology info */
72 gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
73 gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
74 gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
76 /* Turn on all the leds for now */
77 gpio_regs->out = SBCOMMON_GPIO_LEDS;
79 /*--------------------------------------------------------------------+
80 | Initialize EBC CONFIG
81 +-------------------------------------------------------------------*/
83 EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
84 EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
85 EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
86 EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
89 /*--------------------------------------------------------------------+
90 | 1/2 MB FLASH. Initialize bank 0 with default values.
91 +-------------------------------------------------------------------*/
93 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
94 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
95 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
96 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
97 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
98 EBC_BXAP_PEN_DISABLED);
100 mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
101 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
102 /*--------------------------------------------------------------------+
103 | 8KB NVRAM/RTC. Initialize bank 1 with default values.
104 +-------------------------------------------------------------------*/
106 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
107 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
108 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
109 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
110 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
111 EBC_BXAP_PEN_DISABLED);
113 mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
114 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
116 /*--------------------------------------------------------------------+
117 | Compact Flash, uses 2 Chip Selects (2 & 6)
118 +-------------------------------------------------------------------*/
120 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
121 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
122 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
123 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
124 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
125 EBC_BXAP_PEN_DISABLED);
127 mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) |
128 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
130 /*--------------------------------------------------------------------+
131 | KaRef Scan FPGA. Initialize bank 3 with default values.
132 +-------------------------------------------------------------------*/
134 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
135 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
136 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
137 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
138 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
140 mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48200000) |
141 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
143 /*--------------------------------------------------------------------+
144 | MAC A & B for Kamino. OFEM FPGA decodes the addresses
145 | Initialize bank 4 with default values.
146 +-------------------------------------------------------------------*/
148 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
149 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
150 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
151 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
152 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
154 mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) |
155 EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
157 /*--------------------------------------------------------------------+
158 | OFEM FPGA Initialize bank 5 with default values.
159 +-------------------------------------------------------------------*/
161 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
162 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
163 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
164 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
165 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
168 mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48400000) |
169 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
172 /*--------------------------------------------------------------------+
173 | Compact Flash, uses 2 Chip Selects (2 & 6)
174 +-------------------------------------------------------------------*/
176 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
177 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
178 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
179 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
180 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
181 EBC_BXAP_PEN_DISABLED);
183 mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) |
184 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
186 /*--------------------------------------------------------------------+
187 | BME-32. Initialize bank 7 with default values.
188 +-------------------------------------------------------------------*/
190 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
191 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
192 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
193 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
194 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
196 mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) |
197 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
199 /*--------------------------------------------------------------------+
200 * Setup the interrupt controller polarities, triggers, etc.
201 +-------------------------------------------------------------------*/
203 * Because of the interrupt handling rework to handle 440GX interrupts
204 * with the common code, we needed to change names of the UIC registers.
205 * Here the new relationship:
207 * U-Boot name 440GX name
208 * -----------------------
214 mtdcr (UIC1SR, 0xffffffff); /* clear all */
215 mtdcr (UIC1ER, 0x00000000); /* disable all */
216 mtdcr (UIC1CR, 0x00000000); /* all non- critical */
217 mtdcr (UIC1PR, 0xfffffe03); /* polarity */
218 mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */
219 mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
220 mtdcr (UIC1SR, 0xffffffff); /* clear all */
222 mtdcr (UIC2SR, 0xffffffff); /* clear all */
223 mtdcr (UIC2ER, 0x00000000); /* disable all */
224 mtdcr (UIC2CR, 0x00000000); /* all non-critical */
225 mtdcr (UIC2PR, 0xffffc8ff); /* polarity */
226 mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */
227 mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
228 mtdcr (UIC2SR, 0xffffffff); /* clear all */
230 mtdcr (UIC3SR, 0xffffffff); /* clear all */
231 mtdcr (UIC3ER, 0x00000000); /* disable all */
232 mtdcr (UIC3CR, 0x00000000); /* all non-critical */
233 mtdcr (UIC3PR, 0xffff83ff); /* polarity */
234 mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */
235 mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
236 mtdcr (UIC3SR, 0xffffffff); /* clear all */
238 mtdcr (UIC0SR, 0xfc000000); /* clear all */
239 mtdcr (UIC0ER, 0x00000000); /* disable all */
240 mtdcr (UIC0CR, 0x00000000); /* all non-critical */
241 mtdcr (UIC0PR, 0xfc000000);
242 mtdcr (UIC0TR, 0x00000000);
243 mtdcr (UIC0VR, 0x00000001);
251 /*************************************************************************
254 * Dump pertinent info to the console
255 ************************************************************************/
256 int checkboard (void)
259 unsigned char brd_rev, brd_id;
260 unsigned short sernum;
261 unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0;
262 unsigned char ofem_brd_rev, ofem_brd_id;
263 KAREF_FPGA_REGS_ST *karef_ps;
264 OFEM_FPGA_REGS_ST *ofem_ps;
266 karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
267 ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
269 scan_id = (unsigned char)((karef_ps->revision_ul &
270 SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
271 >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
273 scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
274 >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
276 brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
277 >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
279 brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
280 >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
282 ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
283 >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
285 ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
286 >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
288 if (0xF != ofem_brd_id) {
289 ofem_id = (unsigned char)((ofem_ps->revision_ul &
290 SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
291 >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
293 ofem_rev = (unsigned char)((ofem_ps->revision_ul &
294 SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
295 >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
298 get_sys_info (&sysinfo);
300 sernum = sbcommon_get_serial_number();
302 printf ("Board: Sandburst Corporation Kamino Reference Design "
303 "Serial Number: %d\n", sernum);
304 printf ("%s\n", KAREF_U_BOOT_REL_STR);
306 printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
307 if (sbcommon_get_master()) {
308 printf("Slot 0 - Master\nSlave board");
309 if (sbcommon_secondary_present())
310 printf(" present\n");
312 printf(" not detected\n");
314 printf("Slot 1 - Slave\n\n");
317 printf ("ScanFPGA ID:\t0x%02X\tRev: 0x%02X\n", scan_id, scan_rev);
318 printf ("Board Rev:\t0x%02X\tID: 0x%02X\n", brd_rev, brd_id);
319 if(0xF != ofem_brd_id) {
320 printf("OFemFPGA ID:\t0x%02X\tRev: 0x%02X\n", ofem_id, ofem_rev);
321 printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev);
324 /* Fix the ack in the bme 32 */
326 out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
333 /*************************************************************************
336 * Initialize I2C bus one to gain access to the fans
337 ************************************************************************/
338 int misc_init_f (void)
340 /* Turn on fans 3 & 4 */
346 /*************************************************************************
350 ************************************************************************/
351 int misc_init_r (void)
353 unsigned short sernum;
356 KAREF_FPGA_REGS_ST *karef_ps;
357 OFEM_FPGA_REGS_ST *ofem_ps;
359 if(NULL != getenv("secondserial")) {
360 puts("secondserial is set, switching to second serial port\n");
361 setenv("stderr", "serial1");
362 setenv("stdout", "serial1");
363 setenv("stdin", "serial1");
366 setenv("ubrelver", KAREF_U_BOOT_REL_STR);
368 memset(envstr, 0, 255);
369 sprintf (envstr, "Built %s %s by %s",
370 U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
371 setenv("bldstr", envstr);
374 if( getenv("autorecover")) {
375 setenv("autorecover", NULL);
377 sernum = sbcommon_get_serial_number();
379 printf("\nSetting up environment for automatic filesystem recovery\n");
381 * Setup default bootargs
383 memset(envstr, 0, 255);
385 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
386 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
388 setenv("bootargs", envstr);
391 * Setup Default boot command
393 setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
394 "fatload ide 0 8100000 pramdisk;"
395 "bootm 8000000 8100000");
397 printf("Done. Please type allow the system to continue to boot\n");
400 if( getenv("fakeled")) {
401 karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
402 ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
403 ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
404 karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
405 setenv("bootdelay", "-1");
407 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
410 #ifdef CONFIG_HAS_ETH0
411 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
412 board_get_enetaddr(0, enetaddr);
413 eth_setenv_enetaddr("ethaddr", enetaddr);
417 #ifdef CONFIG_HAS_ETH1
418 if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
419 board_get_enetaddr(1, enetaddr);
420 eth_setenv_enetaddr("eth1addr", enetaddr);
424 #ifdef CONFIG_HAS_ETH2
425 if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
426 board_get_enetaddr(2, enetaddr);
427 eth_setenv_enetaddr("eth2addr", enetaddr);
431 #ifdef CONFIG_HAS_ETH3
432 if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
433 board_get_enetaddr(3, enetaddr);
434 eth_setenv_enetaddr("eth3addr", enetaddr);
441 /*************************************************************************
443 ************************************************************************/
444 #ifdef CONFIG_IDE_RESET
445 void ide_set_reset(int on)
447 KAREF_FPGA_REGS_ST *karef_ps;
448 /* TODO: ide reset */
449 karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
452 karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
454 karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
457 #endif /* CONFIG_IDE_RESET */
459 /*************************************************************************
461 ************************************************************************/
464 KAREF_FPGA_REGS_ST *karef_ps;
465 OFEM_FPGA_REGS_ST *ofem_ps;
466 unsigned char ofem_id;
469 /* Ensure we have power all around */
472 karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
474 SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
475 SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
476 SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
477 SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
478 SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
479 SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
480 SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
481 SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
482 SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
484 karef_ps->reset_ul = tmp;
487 * Wait a bit to allow the ofem fpga to get its brains
492 * Check to see if the ofem is there
494 ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
495 >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
498 SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
499 SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
500 SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
502 ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
503 ofem_ps->reset_ul = tmp;
505 ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
508 karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
515 int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
517 unsigned short sernum;
520 sernum = sbcommon_get_serial_number();
522 memset(envstr, 0, 255);
524 * Setup our ip address
526 sprintf(envstr, "10.100.70.%d", sernum);
528 setenv("ipaddr", envstr);
530 * Setup the host ip address
532 setenv("serverip", "10.100.17.10");
535 * Setup default bootargs
537 memset(envstr, 0, 255);
539 sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
540 "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
541 "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
542 "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
543 sernum, sernum, sernum);
545 setenv("bootargs_nfs", envstr);
546 setenv("bootargs", envstr);
551 memset(envstr, 0, 255);
553 sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
554 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
557 setenv("bootargs_cf", envstr);
560 * Setup Default boot command
562 setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
563 setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
566 * Setup compact flash boot command
568 setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
575 int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
577 unsigned short sernum;
580 sernum = sbcommon_get_serial_number();
582 printf("\nSetting up environment for filesystem recovery\n");
584 * Setup default bootargs
586 memset(envstr, 0, 255);
588 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
589 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
591 setenv("bootargs", envstr);
594 * Setup Default boot command
597 setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
598 "fatload ide 0 8100000 pramdisk;"
599 "bootm 8000000 8100000");
601 printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
602 " please type fsrecover.sh<cr>\n");
607 U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
608 "Set environment to factory defaults", "");
610 U_BOOT_CMD(karecover, 1, 1, karefRecover,
611 "Set environment to allow for fs recovery", "");