board/sandburst/karef/karef.c

   1 /*
   2  *  Copyright (C) 2005 Sandburst Corporation
   3  *  Travis B. Sawyer
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <config.h>
  25 #include <common.h>
  26 #include <command.h>
  27 #include "karef.h"
  28 #include "karef_version.h"
  29 #include <asm/processor.h>
  30 #include <asm/io.h>
  31 #include <spd_sdram.h>
  32 #include <i2c.h>
  33 #include "../common/sb_common.h"
  34 #include "../common/ppc440gx_i2c.h"
  35
  36 void fpga_init (void);
  37
  38 KAREF_BOARD_ID_ST board_id_as[] =
  39 {
  40         {"Undefined"},                       /* Not specified */
  41         {"Kamino Reference Design"},
  42         {"Reserved"},                        /* Reserved for future use */
  43         {"Reserved"},                        /* Reserved for future use */
  44 };
  45
  46 KAREF_BOARD_ID_ST ofem_board_id_as[] =
  47 {
  48         {"Undefined"},
  49         {"1x10 + 10x2"},
  50         {"Reserved"},
  51         {"Reserved"},
  52 };
  53
  54 /*************************************************************************
  55  *  board_early_init_f
  56  *
  57  *  Setup chip selects, initialize the Opto-FPGA, initialize
  58  *  interrupt polarity and triggers.
  59  ************************************************************************/
  60 int board_early_init_f (void)
  61 {
  62         ppc440_gpio_regs_t *gpio_regs;
  63
  64         /* Enable GPIO interrupts */
  65         mtsdr(sdr_pfc0, 0x00103E00);
  66
  67         /* Setup access for LEDs, and system topology info */
  68         gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
  69         gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
  70         gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
  71
  72         /* Turn on all the leds for now */
  73         gpio_regs->out = SBCOMMON_GPIO_LEDS;
  74
  75         /*--------------------------------------------------------------------+
  76           | Initialize EBC CONFIG
  77           +-------------------------------------------------------------------*/
  78         mtebc(xbcfg,
  79               EBC_CFG_LE_UNLOCK    | EBC_CFG_PTD_ENABLE |
  80               EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
  81               EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
  82               EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
  83               EBC_CFG_PR_32);
  84
  85         /*--------------------------------------------------------------------+
  86           | 1/2 MB FLASH. Initialize bank 0 with default values.
  87           +-------------------------------------------------------------------*/
  88         mtebc(pb0ap,
  89               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
  90               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
  91               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
  92               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
  93               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
  94               EBC_BXAP_PEN_DISABLED);
  95
  96         mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
  97               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
  98         /*--------------------------------------------------------------------+
  99           | 8KB NVRAM/RTC. Initialize bank 1 with default values.
 100           +-------------------------------------------------------------------*/
 101         mtebc(pb1ap,
 102               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
 103               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 104               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 105               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
 106               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 107               EBC_BXAP_PEN_DISABLED);
 108
 109         mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
 110               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
 111
 112         /*--------------------------------------------------------------------+
 113           | Compact Flash, uses 2 Chip Selects (2 & 6)
 114           +-------------------------------------------------------------------*/
 115         mtebc(pb2ap,
 116               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 117               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 118               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 119               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 120               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 121               EBC_BXAP_PEN_DISABLED);
 122
 123         mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
 124               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 125
 126         /*--------------------------------------------------------------------+
 127           | KaRef Scan FPGA. Initialize bank 3 with default values.
 128           +-------------------------------------------------------------------*/
 129         mtebc(pb5ap,
 130               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 131               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 132               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 133               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 134               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 135
 136         mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
 137               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 138
 139         /*--------------------------------------------------------------------+
 140           | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
 141           | Initialize bank 4 with default values.
 142           +-------------------------------------------------------------------*/
 143         mtebc(pb4ap,
 144               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 145               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 146               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 147               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 148               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 149
 150         mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
 151               EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 152
 153         /*--------------------------------------------------------------------+
 154           | OFEM FPGA  Initialize bank 5 with default values.
 155           +-------------------------------------------------------------------*/
 156         mtebc(pb3ap,
 157               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 158               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 159               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 160               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 161               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 162
 163
 164         mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) |
 165               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 166
 167
 168         /*--------------------------------------------------------------------+
 169           | Compact Flash, uses 2 Chip Selects (2 & 6)
 170           +-------------------------------------------------------------------*/
 171         mtebc(pb6ap,
 172               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 173               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 174               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 175               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 176               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 177               EBC_BXAP_PEN_DISABLED);
 178
 179         mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
 180               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 181
 182         /*--------------------------------------------------------------------+
 183           | BME-32. Initialize bank 7 with default values.
 184           +-------------------------------------------------------------------*/
 185         mtebc(pb7ap,
 186               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 187               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 188               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 189               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 190               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 191
 192         mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
 193               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 194
 195         /*--------------------------------------------------------------------+
 196          * Setup the interrupt controller polarities, triggers, etc.
 197          +-------------------------------------------------------------------*/
 198         mtdcr (uic0sr, 0xffffffff);     /* clear all */
 199         mtdcr (uic0er, 0x00000000);     /* disable all */
 200         mtdcr (uic0cr, 0x00000000);     /* all non- critical */
 201         mtdcr (uic0pr, 0xfffffe03);     /* polarity */
 202         mtdcr (uic0tr, 0x01c00000);     /* trigger edge vs level */
 203         mtdcr (uic0vr, 0x00000001);     /* int31 highest, base=0x000 */
 204         mtdcr (uic0sr, 0xffffffff);     /* clear all */
 205
 206         mtdcr (uic1sr, 0xffffffff);     /* clear all */
 207         mtdcr (uic1er, 0x00000000);     /* disable all */
 208         mtdcr (uic1cr, 0x00000000);     /* all non-critical */
 209         mtdcr (uic1pr, 0xffffc8ff);     /* polarity */
 210         mtdcr (uic1tr, 0x00ff0000);     /* trigger edge vs level */
 211         mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
 212         mtdcr (uic1sr, 0xffffffff);     /* clear all */
 213
 214         mtdcr (uic2sr, 0xffffffff);     /* clear all */
 215         mtdcr (uic2er, 0x00000000);     /* disable all */
 216         mtdcr (uic2cr, 0x00000000);     /* all non-critical */
 217         mtdcr (uic2pr, 0xffff83ff);     /* polarity */
 218         mtdcr (uic2tr, 0x00ff8c0f);     /* trigger edge vs level */
 219         mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
 220         mtdcr (uic2sr, 0xffffffff);     /* clear all */
 221
 222         mtdcr (uicb0sr, 0xfc000000);    /* clear all */
 223         mtdcr (uicb0er, 0x00000000);    /* disable all */
 224         mtdcr (uicb0cr, 0x00000000);    /* all non-critical */
 225         mtdcr (uicb0pr, 0xfc000000);
 226         mtdcr (uicb0tr, 0x00000000);
 227         mtdcr (uicb0vr, 0x00000001);
 228
 229         fpga_init();
 230
 231         return 0;
 232 }
 233
 234
 235 /*************************************************************************
 236  *  checkboard
 237  *
 238  *  Dump pertinent info to the console
 239  ************************************************************************/
 240 int checkboard (void)
 241 {
 242         sys_info_t sysinfo;
 243         unsigned char brd_rev, brd_id;
 244         unsigned short sernum;
 245         unsigned char scan_rev, scan_id, ofem_rev, ofem_id;
 246         unsigned char ofem_brd_rev, ofem_brd_id;
 247         KAREF_FPGA_REGS_ST *karef_ps;
 248         OFEM_FPGA_REGS_ST *ofem_ps;
 249
 250         karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
 251         ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
 252
 253         scan_id = (unsigned char)((karef_ps->revision_ul &
 254                                    SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
 255                                   >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
 256
 257         scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
 258                                    >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
 259
 260         brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
 261                                   >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
 262
 263         brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
 264                                  >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
 265
 266         ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
 267                                       >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
 268
 269         ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
 270                                        >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
 271
 272         if (0xF != ofem_brd_id) {
 273                 ofem_id = (unsigned char)((ofem_ps->revision_ul &
 274                                            SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
 275                                           >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
 276
 277                 ofem_rev = (unsigned char)((ofem_ps->revision_ul &
 278                                             SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
 279                                            >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
 280         }
 281
 282         get_sys_info (&sysinfo);
 283
 284         sernum = sbcommon_get_serial_number();
 285
 286         printf ("Board: Sandburst Corporation Kamino Reference Design "
 287                 "Serial Number: %d\n", sernum);
 288         printf ("%s\n", KAREF_U_BOOT_REL_STR);
 289
 290         printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
 291         if (sbcommon_get_master()) {
 292                 printf("Slot 0 - Master\nSlave board");
 293                 if (sbcommon_secondary_present())
 294                         printf(" present\n");
 295                 else
 296                         printf(" not detected\n");
 297         } else {
 298                 printf("Slot 1 - Slave\n\n");
 299         }
 300
 301         printf ("ScanFPGA ID:\t0x%02X\tRev:  0x%02X\n", scan_id, scan_rev);
 302         printf ("Board Rev:\t0x%02X\tID:   0x%02X\n", brd_rev, brd_id);
 303         if(0xF != ofem_brd_id) {
 304                 printf("OFemFPGA ID:\t0x%02X\tRev:  0x%02X\n", ofem_id, ofem_rev);
 305                 printf("OFEM Board Rev:\t0x%02X\tID:   0x%02X\n", ofem_brd_id, ofem_brd_rev);
 306         }
 307
 308         printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
 309         printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
 310         printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
 311         printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
 312         printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
 313
 314         /* Fix the ack in the bme 32 */
 315         udelay(5000);
 316         out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
 317         asm("eieio");
 318
 319
 320         return (0);
 321 }
 322
 323 /*************************************************************************
 324  *  misc_init_f
 325  *
 326  *  Initialize I2C bus one to gain access to the fans
 327  ************************************************************************/
 328 int misc_init_f (void)
 329 {
 330         /* Turn on i2c bus 1 */
 331         puts ("I2C1:  ");
 332         i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
 333         puts ("ready\n");
 334
 335         /* Turn on fans 3 & 4 */
 336         sbcommon_fans();
 337
 338         return (0);
 339 }
 340
 341 /*************************************************************************
 342  *  misc_init_r
 343  *
 344  *  Do nothing.
 345  ************************************************************************/
 346 int misc_init_r (void)
 347 {
 348         unsigned short sernum;
 349         char envstr[255];
 350         KAREF_FPGA_REGS_ST *karef_ps;
 351         OFEM_FPGA_REGS_ST *ofem_ps;
 352         unsigned char ofem_id;
 353
 354         if(NULL != getenv("secondserial")) {
 355                 puts("secondserial is set, switching to second serial port\n");
 356                 setenv("stderr", "serial1");
 357                 setenv("stdout", "serial1");
 358                 setenv("stdin", "serial1");
 359         }
 360
 361         setenv("ubrelver", KAREF_U_BOOT_REL_STR);
 362
 363         memset(envstr, 0, 255);
 364         sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
 365         setenv("bldstr", envstr);
 366         saveenv();
 367
 368         if( getenv("autorecover")) {
 369                 setenv("autorecover", NULL);
 370                 saveenv();
 371                 sernum = sbcommon_get_serial_number();
 372
 373                 printf("\nSetting up environment for automatic filesystem recovery\n");
 374                 /*
 375                  * Setup default bootargs
 376                  */
 377                 memset(envstr, 0, 255);
 378
 379                 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 380                         "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
 381                         sernum, sernum);
 382                 setenv("bootargs", envstr);
 383
 384                 /*
 385                  * Setup Default boot command
 386                  */
 387                 setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
 388                        "fatload ide 0 8100000 pramdisk;"
 389                        "bootm 8000000 8100000");
 390
 391                 printf("Done.  Please type allow the system to continue to boot\n");
 392         }
 393
 394         if( getenv("fakeled")) {
 395                 karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
 396                 ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
 397                 ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
 398                 karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
 399                 setenv("bootdelay", "-1");
 400                 saveenv();
 401                 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
 402         }
 403
 404         return (0);
 405 }
 406
 407 /*************************************************************************
 408  *  ide_set_reset
 409  ************************************************************************/
 410 #ifdef CONFIG_IDE_RESET
 411 void ide_set_reset(int on)
 412 {
 413         KAREF_FPGA_REGS_ST *karef_ps;
 414         /* TODO: ide reset */
 415         karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
 416
 417         if (on) {
 418                 karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
 419         } else {
 420                 karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
 421         }
 422 }
 423 #endif /* CONFIG_IDE_RESET */
 424
 425 /*************************************************************************
 426  *  fpga_init
 427  ************************************************************************/
 428 void fpga_init(void)
 429 {
 430         KAREF_FPGA_REGS_ST *karef_ps;
 431         OFEM_FPGA_REGS_ST *ofem_ps;
 432         unsigned char ofem_id;
 433         unsigned long tmp;
 434
 435         /* Ensure we have power all around */
 436         udelay(500);
 437
 438         karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
 439         tmp =
 440                 SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
 441                 SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
 442                 SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
 443                 SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
 444                 SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
 445                 SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
 446                 SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
 447                 SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
 448                 SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
 449
 450         karef_ps->reset_ul = tmp;
 451
 452         /*
 453          * Wait a bit to allow the ofem fpga to get its brains
 454          */
 455         udelay(5000);
 456
 457         /*
 458          * Check to see if the ofem is there
 459          */
 460         ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
 461                                   >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
 462         if(0xF != ofem_id) {
 463                 tmp =
 464                         SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
 465                         SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
 466                         SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
 467
 468                 ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
 469                 ofem_ps->reset_ul = tmp;
 470
 471                 ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
 472         }
 473
 474         karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
 475
 476         asm("eieio");
 477
 478         return;
 479 }
 480
 481 int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 482 {
 483         unsigned short sernum;
 484         char envstr[255];
 485
 486         sernum = sbcommon_get_serial_number();
 487
 488         memset(envstr, 0, 255);
 489         /*
 490          * Setup our ip address
 491          */
 492         sprintf(envstr, "10.100.70.%d", sernum);
 493
 494         setenv("ipaddr", envstr);
 495         /*
 496          * Setup the host ip address
 497          */
 498         setenv("serverip", "10.100.17.10");
 499
 500         /*
 501          * Setup default bootargs
 502          */
 503         memset(envstr, 0, 255);
 504
 505         sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
 506                 "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
 507                 "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
 508                 "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
 509                 sernum, sernum, sernum);
 510
 511         setenv("bootargs_nfs", envstr);
 512         setenv("bootargs", envstr);
 513
 514         /*
 515          * Setup CF bootargs
 516          */
 517         memset(envstr, 0, 255);
 518
 519         sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
 520                 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
 521                 sernum, sernum);
 522
 523         setenv("bootargs_cf", envstr);
 524
 525         /*
 526          * Setup Default boot command
 527          */
 528         setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
 529         setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
 530
 531         /*
 532          * Setup compact flash boot command
 533          */
 534         setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
 535
 536         saveenv();
 537
 538         return(1);
 539 }
 540
 541 int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 542 {
 543         unsigned short sernum;
 544         char envstr[255];
 545
 546         sernum = sbcommon_get_serial_number();
 547
 548         printf("\nSetting up environment for filesystem recovery\n");
 549         /*
 550          * Setup default bootargs
 551          */
 552         memset(envstr, 0, 255);
 553
 554         sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 555                 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
 556                 sernum, sernum);
 557         setenv("bootargs", envstr);
 558
 559         /*
 560          * Setup Default boot command
 561          */
 562
 563         setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
 564                "fatload ide 0 8100000 pramdisk;"
 565                "bootm 8000000 8100000");
 566
 567         printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
 568                " please type fsrecover.sh<cr>\n");
 569
 570         return(1);
 571 }
 572
 573 U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
 574            "kasetup - Set environment to factory defaults\n", NULL);
 575
 576 U_BOOT_CMD(karecover, 1, 1, karefRecover,
 577            "karecover - Set environment to allow for fs recovery\n", NULL);