2 * Lowlevel setup for universal board based on EXYNOS4210
4 * Copyright (C) 2010 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/cpu.h>
29 #include <asm/arch/clock.h>
35 * r7 has GPIO part1 base 0x11400000
36 * r6 has GPIO part2 base 0x11000000
43 /* r5 has always zero */
46 ldr r7, =EXYNOS4_GPIO_PART1_BASE
47 ldr r6, =EXYNOS4_GPIO_PART2_BASE
50 ldr r0, =EXYNOS4_SYSTIMER_BASE
58 /* PMIC manual reset */
59 /* nPOWER: XEINT_23: GPX2[7] */
60 add r0, r6, #0xC40 @ EXYNOS4_GPIO_X2_OFFSET
62 bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
63 orr r1, r1, #(0x1 << 28) @ Output
67 orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
70 /* init system clock */
73 /* Disable Watchdog */
74 ldr r0, =EXYNOS4_WATCHDOG_BASE @0x10060000
92 * uart_asm_init: Initialize UART's pins
96 * setup UART0-UART4 GPIOs (part1)
97 * GPA1CON[3] = I2C_3_SCL (3)
98 * GPA1CON[2] = I2C_3_SDA (3)
102 str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET
104 str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET
106 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
107 add r0, r6, #0x1A0 @ EXYNOS4_GPIO_Y4_OFFSET
109 bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
110 orr r1, r1, #(0x1 << 28)
114 bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
115 orr r1, r1, #(0x3 << 14) @ Pull-up enabled
119 orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
128 ldr r0, =EXYNOS4_CLOCK_BASE
130 /* APLL(1), MPLL(1), CORE(0), HPM(0) */
132 ldr r2, =0x14200 @ CLK_SRC_CPU
142 * MUX_ONENAND_SEL[28] 0: DOUT133, 1: DOUT166
143 * MUX_VPLL_SEL[8] 0: FINPLL, 1: FOUTVPLL
144 * MUX_EPLL_SEL[4] 0: FINPLL, 1: FOUTEPLL
147 ldr r2, =0x0C210 @ CLK_SRC_TOP
150 /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
152 ldr r2, =0x0C240 @ CLK_SRC_FSYS
154 /* UART[0:5], PWM: SCLKMPLL(6) */
156 ldr r2, =0x0C250 @ CLK_SRC_PERIL0_OFFSET
159 /* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */
161 ldr r2, =0x14500 @ CLK_DIV_CPU0
163 /* CPU1: COPY, HPM */
165 ldr r2, =0x14504 @ CLK_DIV_CPU1
167 /* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */
169 ldr r2, =0x10500 @ CLK_DIV_DMC0
171 /* DMC1: PWI, DVSEM, DPM */
173 ldr r2, =0x10504 @ CLK_DIV_DMC1
175 /* LEFTBUS: GDL, GPL */
177 ldr r2, =0x04500 @ CLK_DIV_LEFTBUS
179 /* RIGHHTBUS: GDR, GPR */
181 ldr r2, =0x08500 @ CLK_DIV_RIGHTBUS
185 * ONENAND_RATIOD[18:16]: 0 SCLK_ONENAND = MOUTONENAND / (n + 1)
186 * ACLK_200, ACLK_100, ACLK_160, ACLK_133,
189 ldr r2, =0x0C510 @ CLK_DIV_TOP
192 ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
193 ldr r2, =0x0C544 @ CLK_DIV_FSYS1
196 ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
197 ldr r2, =0x0C548 @ CLK_DIV_FSYS2
200 ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */
201 ldr r2, =0x0C54C @ CLK_DIV_FSYS3
205 ldr r2, =0x0C550 @ CLK_DIV_PERIL0
207 /* SLIMBUS: ???, PWM */
209 ldr r2, =0x0C55C @ CLK_DIV_PERIL3
214 ldr r2, =0x14000 @ APLL_LOCK
216 ldr r2, =0x14008 @ MPLL_LOCK
218 ldr r2, =0x0C010 @ EPLL_LOCK
220 ldr r2, =0x0C020 @ VPLL_LOCK
225 ldr r2, =0x14104 @ APLL_CON1
227 ldr r1, =0x80c80601 @ 800MHz
228 ldr r2, =0x14100 @ APLL_CON0
232 ldr r2, =0x1410C @ MPLL_CON1
234 ldr r1, =0x80c80601 @ 800MHz
235 ldr r2, =0x14108 @ MPLL_CON0
239 ldr r2, =0x0C114 @ EPLL_CON1
241 ldr r1, =0x80300302 @ 96MHz
242 ldr r2, =0x0C110 @ EPLL_CON0
246 ldr r2, =0x0C124 @ VPLL_CON1
248 ldr r1, =0x80350302 @ 108MHz
249 ldr r2, =0x0C120 @ VPLL_CON0
253 * SMMUJPEG[11], JPEG[6], CSIS1[5] : 0111 1001
257 ldr r2, =0x0C920 @ CLK_GATE_IP_CAM
262 ldr r2, =0x0C924 @ CLK_GATE_IP_VP
267 ldr r2, =0x0C928 @ CLK_GATE_IP_MFC
272 ldr r2, =0x0C92C @ CLK_GATE_IP_G3D
277 ldr r2, =0x0C930 @ CLK_GATE_IP_IMAGE
280 /* DSIM0[3], MDNIE0[2], MIE0[1] : 0001 */
282 ldr r2, =0x0C934 @ CLK_GATE_IP_LCD0
287 ldr r2, =0x0C938 @ CLK_GATE_IP_LCD1
291 * SMMUPCIE[18], NFCON[16] : 1111 1010
292 * PCIE[14], SATA[10], SDMMC43[9:8] : 1011 1000
293 * SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2] : 1010 0011
296 ldr r2, =0x0C940 @ CLK_GATE_IP_FSYS
301 ldr r2, =0x0C94C @ CLK_GATE_IP_GPS
305 * AC97[27], SPDIF[26], SLIMBUS[25] : 1111 0001
306 * I2C2[8] : 1111 1110
309 ldr r2, =0x0C950 @ CLK_GATE_IP_PERIL
313 * KEYIF[16] : 1111 1110
316 ldr r2, =0x0C960 @ CLK_GATE_IP_PERIR
319 /* LCD1[5], G3D[3], MFC[2], TV[1] : 1101 0001 */
321 ldr r2, =0x0C970 @ CLK_GATE_BLOCK
329 ldr r0, =EXYNOS4_POWER_BASE @ 0x10020000
331 ldr r2, =0x330C @ PS_HOLD_CONTROL
333 orr r1, r1, #(0x3 << 8) @ Data High, Output En
338 str r5, [r2, #0xC20] @ TV_CONFIGURATION
339 str r5, [r2, #0xC40] @ MFC_CONFIGURATION
340 str r5, [r2, #0xC60] @ G3D_CONFIGURATION
341 str r5, [r2, #0xCA0] @ LCD1_CONFIGURATION
342 str r5, [r2, #0xCE0] @ GPS_CONFIGURATION
354 str r1, [r0, #0x0804]
355 str r1, [r0, #0x0810]
356 str r1, [r0, #0x081C]
357 str r1, [r0, #0x0828]
363 str r1, [r0, #0x0804]
364 str r1, [r0, #0x0810]
365 str r1, [r0, #0x081C]
366 str r1, [r0, #0x0828]
372 str r1, [r0, #0x0804]
373 str r1, [r0, #0x0810]
374 str r1, [r0, #0x081C]
375 str r1, [r0, #0x0828]
381 str r1, [r0, #0x0804]
382 str r1, [r0, #0x0810]
383 str r1, [r0, #0x081C]
384 str r1, [r0, #0x0828]
390 str r1, [r0, #0x0804]
391 str r1, [r0, #0x0810]
392 str r1, [r0, #0x081C]
393 str r1, [r0, #0x0828]