board/samsung/universal_c100/mem_setup.S

   1 /*
   2  * Copyright (C) 2009 Samsung Electrnoics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26
  27 #define NEW_MEMORY_TIMING
  28 #undef NEW_MEMORY_TIMING
  29
  30         .globl mem_ctrl_asm_init
  31 mem_ctrl_asm_init:
  32         cmp     r7, r8
  33
  34 #ifdef NEW_MEMORY_TIMING
  35         /* CLOCK_POWER_BASE */
  36         ldrne   r0, =0xE0100000
  37         orrne   r0, r0, #0x6200
  38         orrne   r0, r0, #0x0008
  39         ldrne   r1, =0x00000000         @ 0 : SCLK_ONEDRAM, 1 : HCLK200
  40         strne   r1, [r0]
  41
  42         /* ASYNC_MSYS_DMC0_BASE */
  43         ldrne   r0, =0xF1E00000
  44         ldrne   r1, =0x0
  45         strne   r1, [r0, #0x0]
  46         ldrne   r1, =0x0
  47         str     r1, [r0, #0xC]
  48 #endif
  49
  50         ldreq   r0, =S5PC100_DMC_BASE                   @ 0xE6000000
  51         ldrne   r0, =S5PC110_DMC0_BASE                  @ 0xF0000000
  52         ldrne   r6, =S5PC110_DMC1_BASE                  @ 0xF1400000
  53
  54         /* DLL parameter setting */
  55 #ifdef NEW_MEMORY_TIMING
  56         ldr     r1, =0x003B3B00
  57 #else
  58         ldr     r1, =0x50101000
  59 #endif
  60         str     r1, [r0, #0x018]                        @ PHYCONTROL0_OFFSET
  61         strne   r1, [r6, #0x018]                        @ PHYCONTROL0_OFFSET
  62 #ifdef NEW_MEMORY_TIMING
  63         ldr     r1, =0x00000004
  64 #else
  65         ldr     r1, =0x000000f4
  66 #endif
  67         str     r1, [r0, #0x01C]                        @ PHYCONTROL1_OFFSET
  68         strne   r1, [r6, #0x01C]                        @ PHYCONTROL1_OFFSET
  69         ldreq   r1, =0x0
  70         streq   r1, [r0, #0x020]                        @ PHYCONTROL2_OFFSET
  71
  72         /* DLL on */
  73 #ifdef NEW_MEMORY_TIMING
  74         ldr     r1, =0x003B3B02
  75 #else
  76         ldr     r1, =0x50101002
  77 #endif
  78         str     r1, [r0, #0x018]                        @ PHYCONTROL0_OFFSET
  79         strne   r1, [r6, #0x018]                        @ PHYCONTROL0_OFFSET
  80
  81         /* DLL start */
  82 #ifdef NEW_MEMORY_TIMING
  83         ldr     r1, =0x003B3B03
  84 #else
  85         ldr     r1, =0x50101003
  86 #endif
  87         str     r1, [r0, #0x018]                        @ PHYCONTROL0_OFFSET
  88         strne   r1, [r6, #0x018]                        @ PHYCONTROL0_OFFSET
  89
  90         mov     r2, #0x4000
  91 wait:   subs    r2, r2, #0x1
  92         cmp     r2, #0x0
  93         bne     wait
  94
  95         cmp     r7, r8
  96         /* Force value locking for DLL off */
  97 #ifdef NEW_MEMORY_TIMING
  98         ldr     r1, =0x6A3B3B01
  99 #endif
 100         str     r1, [r0, #0x018]                        @ PHYCONTROL0_OFFSET
 101         strne   r1, [r6, #0x018]                        @ PHYCONTROL0_OFFSET
 102
 103         /* DLL off */
 104 #ifdef NEW_MEMORY_TIMING
 105         ldr     r1, =0x6A3B3B09
 106 #else
 107         ldr     r1, =0x50101009
 108 #endif
 109         str     r1, [r0, #0x018]                        @ PHYCONTROL0_OFFSET
 110         strne   r1, [r6, #0x018]                        @ PHYCONTROL0_OFFSET
 111
 112         /* auto refresh off */
 113 #ifdef NEW_MEMORY_TIMING
 114         ldr     r1, =0x0FFF10B0
 115         ldr     r2, =0x0FFF10B0
 116 #else
 117         ldr     r1, =0xff001010 | (1 << 7)
 118         ldr     r2, =0xff001010 | (1 << 7)
 119 #endif
 120         str     r1, [r0, #0x000]                        @ CONCONTROL_OFFSET
 121         strne   r2, [r6, #0x000]                        @ CONCONTROL_OFFSET
 122
 123         /*
 124          * Burst Length 4, 2 chips, 32-bit, LPDDR
 125          * OFF: dynamic self refresh, force precharge, dynamic power down off
 126          */
 127 #ifdef NEW_MEMORY_TIMING
 128         ldr     r1, =0x00202100
 129         ldr     r2, =0x00212100
 130 #else
 131         ldr     r1, =0x00212100
 132         ldr     r2, =0x00212100
 133 #endif
 134         str     r1, [r0, #0x004]                        @ MEMCONTROL_OFFSET
 135         strne   r2, [r6, #0x004]                        @ MEMCONTROL_OFFSET
 136
 137         /*
 138          * Note:
 139          * If Bank0 has Mobile RAM we place it at 0x3800'0000 (s5pc100 only)
 140          * So finally Bank1 OneDRAM should address start at at 0x3000'0000
 141          */
 142
 143         /*
 144          * DMC0: CS0 : S5PC100/S5PC110
 145          * 0x30 -> 0x30000000
 146          * 0xf8 -> 0x37FFFFFF
 147          * [15:12] 0: Linear
 148          * [11:8 ] 2: 9 bits
 149          * [ 7:4 ] 2: 14 bits
 150          * [ 3:0 ] 2: 4 banks
 151          */
 152         ldr     r3, =0x30f80222
 153         ldr     r4, =0x40f00222
 154 swap_memory:
 155         str     r3, [r0, #0x008]                        @ MEMCONFIG0_OFFSET
 156         str     r4, [r0, #0x00C]                        @ dummy write
 157
 158         /*
 159          * DMC1: CS0 : S5PC110
 160          * 0x40 -> 0x40000000
 161          * 0xf8 -> 0x47FFFFFF (1Gib)
 162          * 0x40 -> 0x40000000
 163          * 0xf0 -> 0x4FFFFFFF (2Gib)
 164          * [15:12] 0: Linear
 165          * [11:8 ] 2: 9 bits  - Col (1Gib)
 166          * [11:8 ] 3: 10 bits - Col (2Gib)
 167          * [ 7:4 ] 2: 14 bits - Row
 168          * [ 3:0 ] 2: 4 banks
 169          */
 170         /* Default : 2GiB */
 171         ldr     r4, =0x40f01322                         @ 2Gib: MCP B
 172         ldr     r5, =0x50f81312                         @ dummy: MCP D
 173         cmp     r9, #1
 174         ldreq   r4, =0x40f81222                         @ 1Gib: MCP A
 175         cmp     r9, #3
 176         ldreq   r5, =0x50f81312                         @ 2Gib + 1Gib: MCP D
 177         cmp     r9, #4
 178         ldreq   r5, =0x50f01312                         @ 2Gib + 2Gib: MCP E
 179
 180         cmp     r7, r8
 181         strne   r4, [r6, #0x008]                        @ MEMCONFIG0_OFFSET
 182         strne   r5, [r6, #0x00C]                        @ MEMCONFIG1_OFFSET
 183
 184         /*
 185          * DMC0: CS1: S5PC100
 186          * 0x38 -> 0x38000000
 187          * 0xf8 -> 0x3fFFFFFF
 188          * [15:12] 0: Linear
 189          * [11:8 ] 2: 9 bits
 190          * [ 7:4 ] 2: 14 bits
 191          * [ 3:0 ] 2: 4 banks
 192          */
 193         eoreq   r3, r3, #0x08000000
 194         streq   r3, [r0, #0xc]                          @ MEMCONFIG1_OFFSET
 195
 196 #ifdef NEW_MEMORY_TIMING
 197         ldr     r1, =0xFF000000
 198 #else
 199         ldr     r1, =0x20000000
 200 #endif
 201         str     r1, [r0, #0x014]                        @ PRECHCONFIG_OFFSET
 202         strne   r1, [r0, #0x014]                        @ PRECHCONFIG_OFFSET
 203         strne   r1, [r6, #0x014]                        @ PRECHCONFIG_OFFSET
 204
 205         /*
 206          * S5PC100:
 207          * DMC:  CS0: 166MHz
 208          *       CS1: 166MHz
 209          * S5PC110:
 210          * DMC0: CS0: 166MHz
 211          * DMC1: CS0: 200MHz
 212          *
 213          * 7.8us * 200MHz %LE %LONG1560(0x618)
 214          * 7.8us * 166MHz %LE %LONG1294(0x50E)
 215          * 7.8us * 133MHz %LE %LONG1038(0x40E),
 216          * 7.8us * 100MHz %LE %LONG780(0x30C),
 217          */
 218         ldr     r1, =0x0000050E
 219         str     r1, [r0, #0x030]                        @ TIMINGAREF_OFFSET
 220         ldrne   r1, =0x00000618
 221         strne   r1, [r6, #0x030]                        @ TIMINGAREF_OFFSET
 222
 223         ldr     r1, =0x14233287
 224         str     r1, [r0, #0x034]                        @ TIMINGROW_OFFSET
 225         ldrne   r1, =0x182332c8
 226         strne   r1, [r6, #0x034]                        @ TIMINGROW_OFFSET
 227
 228         ldr     r1, =0x12130005
 229         str     r1, [r0, #0x038]                        @ TIMINGDATA_OFFSET
 230         ldrne   r1, =0x13130005
 231         strne   r1, [r6, #0x038]                        @ TIMINGDATA_OFFSET
 232
 233         ldr     r1, =0x0E140222
 234         str     r1, [r0, #0x03C]                        @ TIMINGPOWER_OFFSET
 235         ldrne   r1, =0x0E180222
 236         strne   r1, [r6, #0x03C]                        @ TIMINGPOWER_OFFSET
 237
 238         /* chip0 Deselect */
 239         ldr     r1, =0x07000000
 240         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 241         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 242
 243         /* chip0 PALL */
 244         ldr     r1, =0x01000000
 245         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 246         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 247
 248         /* chip0 REFA */
 249         ldr     r1, =0x05000000
 250         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 251         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 252         /* chip0 REFA */
 253         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 254         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 255
 256         /* chip0 MRS */
 257         ldr     r1, =0x00000032
 258         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 259         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 260
 261         /* chip0 EMRS */
 262         ldr     r1, =0x00020020
 263         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 264         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 265
 266         /* chip1 Deselect */
 267         ldr     r1, =0x07100000
 268         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 269         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 270
 271         /* chip1 PALL */
 272         ldr     r1, =0x01100000
 273         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 274         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 275
 276         /* chip1 REFA */
 277         ldr     r1, =0x05100000
 278         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 279         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 280         /* chip1 REFA */
 281         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 282         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 283
 284         /* chip1 MRS */
 285         ldr     r1, =0x00100032
 286         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 287         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 288
 289         /* chip1 EMRS */
 290         ldr     r1, =0x00120020
 291         str     r1, [r0, #0x010]                        @ DIRECTCMD_OFFSET
 292         strne   r1, [r6, #0x010]                        @ DIRECTCMD_OFFSET
 293
 294         /* auto refresh on */
 295 #ifdef NEW_MEMORY_TIMING
 296         ldr     r1, =0x0FFF10B0
 297 #else
 298         ldr     r1, =0xFF002030 | (1 << 7)
 299 #endif
 300         str     r1, [r0, #0x000]                        @ CONCONTROL_OFFSET
 301         strne   r1, [r6, #0x000]                        @ CONCONTROL_OFFSET
 302
 303         /* PwrdnConfig */
 304 #ifdef NEW_MEMORY_TIMING
 305         ldr     r1, =0xFFFF00FF
 306 #else
 307         ldr     r1, =0x00100002
 308 #endif
 309         str     r1, [r0, #0x028]                        @ PWRDNCONFIG_OFFSET
 310         strne   r1, [r6, #0x028]                        @ PWRDNCONFIG_OFFSET
 311
 312 #ifdef NEW_MEMORY_TIMING
 313         /* DMC0: 1 chip, DMC1: 2 chips */
 314         ldr     r1, =0x00202113
 315         ldr     r2, =0x00212113
 316 #else
 317         ldr     r1, =0x00212113
 318 #endif
 319         str     r1, [r0, #0x004]                        @ MEMCONTROL_OFFSET
 320         strne   r1, [r6, #0x004]                        @ MEMCONTROL_OFFSET
 321
 322         /* Skip when S5PC110 */
 323         bne     1f
 324
 325         /* Check OneDRAM access area at s5pc100 */
 326         ldreq   r3, =0x38f80222
 327         ldreq   r1, =0x37ffff00
 328         str     r3, [r1]
 329         ldr     r2, [r1]
 330         cmp     r2, r3
 331         beq     swap_memory
 332 1:
 333         mov     pc, lr
 334
 335         .ltorg