2 * Copyright (C) 2009 Samsung Electrnoics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Kyungmin Park <kyungmin.park@samsung.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #define NEW_MEMORY_TIMING
28 #undef NEW_MEMORY_TIMING
30 .globl mem_ctrl_asm_init
34 #ifdef NEW_MEMORY_TIMING
35 /* CLOCK_POWER_BASE */
39 ldrne r1, =0x00000000 @ 0 : SCLK_ONEDRAM, 1 : HCLK200
42 /* ASYNC_MSYS_DMC0_BASE */
50 ldreq r0, =S5PC100_DMC_BASE @ 0xE6000000
51 ldrne r0, =S5PC110_DMC0_BASE @ 0xF0000000
52 ldrne r6, =S5PC110_DMC1_BASE @ 0xF1400000
54 /* DLL parameter setting */
55 #ifdef NEW_MEMORY_TIMING
60 str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
61 strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
62 #ifdef NEW_MEMORY_TIMING
67 str r1, [r0, #0x01C] @ PHYCONTROL1_OFFSET
68 strne r1, [r6, #0x01C] @ PHYCONTROL1_OFFSET
70 streq r1, [r0, #0x020] @ PHYCONTROL2_OFFSET
73 #ifdef NEW_MEMORY_TIMING
78 str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
79 strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
82 #ifdef NEW_MEMORY_TIMING
87 str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
88 strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
91 wait: subs r2, r2, #0x1
96 /* Force value locking for DLL off */
97 #ifdef NEW_MEMORY_TIMING
100 str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
101 strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
104 #ifdef NEW_MEMORY_TIMING
109 str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET
110 strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET
112 /* auto refresh off */
113 #ifdef NEW_MEMORY_TIMING
117 ldr r1, =0xff001010 | (1 << 7)
118 ldr r2, =0xff001010 | (1 << 7)
120 str r1, [r0, #0x000] @ CONCONTROL_OFFSET
121 strne r2, [r6, #0x000] @ CONCONTROL_OFFSET
124 * Burst Length 4, 2 chips, 32-bit, LPDDR
125 * OFF: dynamic self refresh, force precharge, dynamic power down off
127 #ifdef NEW_MEMORY_TIMING
134 str r1, [r0, #0x004] @ MEMCONTROL_OFFSET
135 strne r2, [r6, #0x004] @ MEMCONTROL_OFFSET
139 * If Bank0 has Mobile RAM we place it at 0x3800'0000 (s5pc100 only)
140 * So finally Bank1 OneDRAM should address start at at 0x3000'0000
144 * DMC0: CS0 : S5PC100/S5PC110
155 str r3, [r0, #0x008] @ MEMCONFIG0_OFFSET
156 str r4, [r0, #0x00C] @ dummy write
159 * DMC1: CS0 : S5PC110
161 * 0xf8 -> 0x47FFFFFF (1Gib)
163 * 0xf0 -> 0x4FFFFFFF (2Gib)
165 * [11:8 ] 2: 9 bits - Col (1Gib)
166 * [11:8 ] 3: 10 bits - Col (2Gib)
167 * [ 7:4 ] 2: 14 bits - Row
171 ldr r4, =0x40f01322 @ 2Gib: MCP B
172 ldr r5, =0x50f81312 @ dummy: MCP D
174 ldreq r4, =0x40f81222 @ 1Gib: MCP A
176 ldreq r5, =0x50f81312 @ 2Gib + 1Gib: MCP D
178 ldreq r5, =0x50f01312 @ 2Gib + 2Gib: MCP E
181 strne r4, [r6, #0x008] @ MEMCONFIG0_OFFSET
182 strne r5, [r6, #0x00C] @ MEMCONFIG1_OFFSET
193 eoreq r3, r3, #0x08000000
194 streq r3, [r0, #0xc] @ MEMCONFIG1_OFFSET
196 #ifdef NEW_MEMORY_TIMING
201 str r1, [r0, #0x014] @ PRECHCONFIG_OFFSET
202 strne r1, [r0, #0x014] @ PRECHCONFIG_OFFSET
203 strne r1, [r6, #0x014] @ PRECHCONFIG_OFFSET
213 * 7.8us * 200MHz %LE %LONG1560(0x618)
214 * 7.8us * 166MHz %LE %LONG1294(0x50E)
215 * 7.8us * 133MHz %LE %LONG1038(0x40E),
216 * 7.8us * 100MHz %LE %LONG780(0x30C),
219 str r1, [r0, #0x030] @ TIMINGAREF_OFFSET
220 ldrne r1, =0x00000618
221 strne r1, [r6, #0x030] @ TIMINGAREF_OFFSET
224 str r1, [r0, #0x034] @ TIMINGROW_OFFSET
225 ldrne r1, =0x182332c8
226 strne r1, [r6, #0x034] @ TIMINGROW_OFFSET
229 str r1, [r0, #0x038] @ TIMINGDATA_OFFSET
230 ldrne r1, =0x13130005
231 strne r1, [r6, #0x038] @ TIMINGDATA_OFFSET
234 str r1, [r0, #0x03C] @ TIMINGPOWER_OFFSET
235 ldrne r1, =0x0E180222
236 strne r1, [r6, #0x03C] @ TIMINGPOWER_OFFSET
240 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
241 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
245 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
246 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
250 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
251 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
253 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
254 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
258 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
259 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
263 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
264 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
268 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
269 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
273 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
274 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
278 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
279 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
281 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
282 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
286 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
287 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
291 str r1, [r0, #0x010] @ DIRECTCMD_OFFSET
292 strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET
294 /* auto refresh on */
295 #ifdef NEW_MEMORY_TIMING
298 ldr r1, =0xFF002030 | (1 << 7)
300 str r1, [r0, #0x000] @ CONCONTROL_OFFSET
301 strne r1, [r6, #0x000] @ CONCONTROL_OFFSET
304 #ifdef NEW_MEMORY_TIMING
309 str r1, [r0, #0x028] @ PWRDNCONFIG_OFFSET
310 strne r1, [r6, #0x028] @ PWRDNCONFIG_OFFSET
312 #ifdef NEW_MEMORY_TIMING
313 /* DMC0: 1 chip, DMC1: 2 chips */
319 str r1, [r0, #0x004] @ MEMCONTROL_OFFSET
320 strne r1, [r6, #0x004] @ MEMCONTROL_OFFSET
322 /* Skip when S5PC110 */
325 /* Check OneDRAM access area at s5pc100 */
326 ldreq r3, =0x38f80222
327 ldreq r1, =0x37ffff00