2 * Copyright (C) 2011 Samsung Electronics
3 * Heungjun Kim <riverful.kim@samsung.com>
4 * Kyungmin Park <kyungmin.park@samsung.com>
5 * Donghwa Lee <dh09.lee@samsung.com>
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/gpio.h>
15 #include <asm/arch/mmc.h>
16 #include <asm/arch/pinmux.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/clk.h>
19 #include <asm/arch/mipi_dsim.h>
20 #include <asm/arch/watchdog.h>
21 #include <asm/arch/power.h>
22 #include <power/pmic.h>
23 #include <usb/s3c_udc.h>
24 #include <power/max8997_pmic.h>
26 #include <power/max8997_muic.h>
27 #include <power/battery.h>
28 #include <power/max17042_fg.h>
30 #include <usb_mass_storage.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 unsigned int board_rev;
38 #ifdef CONFIG_REVISION_TAG
39 u32 get_board_rev(void)
45 static void check_hw_revision(void);
46 struct s3c_plat_otg_data s5pc210_otg_data;
50 gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR;
53 printf("HW Revision:\t0x%x\n", board_rev);
58 void i2c_init_board(void)
60 struct exynos4_gpio_part1 *gpio1 =
61 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
62 struct exynos4_gpio_part2 *gpio2 =
63 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
65 /* I2C_5 -> PMIC -> Adapter 0 */
66 s5p_gpio_direction_output(&gpio1->b, 7, 1);
67 s5p_gpio_direction_output(&gpio1->b, 6, 1);
68 /* I2C_9 -> FG -> Adapter 1 */
69 s5p_gpio_direction_output(&gpio2->y4, 0, 1);
70 s5p_gpio_direction_output(&gpio2->y4, 1, 1);
73 static void trats_low_power_mode(void)
75 struct exynos4_clock *clk =
76 (struct exynos4_clock *)samsung_get_base_clock();
77 struct exynos4_power *pwr =
78 (struct exynos4_power *)samsung_get_base_power();
80 /* Power down CORE1 */
81 /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
82 writel(0x0, &pwr->arm_core1_configuration);
84 /* Change the APLL frequency */
85 /* ENABLE (1 enable) | LOCKED (1 locked) */
87 /* FSEL | MDIV | PDIV | SDIV */
88 /* [27] | [25:16] | [13:8] | [2:0] */
89 writel(0xa0c80604, &clk->apll_con0);
91 /* Change CPU0 clock divider */
92 /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */
93 /* [30:28] | [26:24] | [22:20] | [18:16] */
94 /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */
95 /* [14:12] | [10:8] | [6:4] | [2:0] */
96 writel(0x00000100, &clk->div_cpu0);
98 /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
99 while (readl(&clk->div_stat_cpu0) & 0x1111111)
102 /* Change clock divider ratio for DMC */
103 /* DMCP_RATIO | DMCD_RATIO */
104 /* [22:20] | [18:16] */
105 /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */
106 /* [14:12] | [10:8] | [6:4] | [2:0] */
107 writel(0x13113117, &clk->div_dmc0);
109 /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
110 while (readl(&clk->div_stat_dmc0) & 0x11111111)
113 /* Turn off unnecessary power domains */
114 writel(0x0, &pwr->xxti_configuration); /* XXTI */
115 writel(0x0, &pwr->cam_configuration); /* CAM */
116 writel(0x0, &pwr->tv_configuration); /* TV */
117 writel(0x0, &pwr->mfc_configuration); /* MFC */
118 writel(0x0, &pwr->g3d_configuration); /* G3D */
119 writel(0x0, &pwr->gps_configuration); /* GPS */
120 writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */
122 /* Turn off unnecessary clocks */
123 writel(0x0, &clk->gate_ip_cam); /* CAM */
124 writel(0x0, &clk->gate_ip_tv); /* TV */
125 writel(0x0, &clk->gate_ip_mfc); /* MFC */
126 writel(0x0, &clk->gate_ip_g3d); /* G3D */
127 writel(0x0, &clk->gate_ip_image); /* IMAGE */
128 writel(0x0, &clk->gate_ip_gps); /* GPS */
131 static int pmic_init_max8997(void)
133 struct pmic *p = pmic_get("MAX8997_PMIC");
140 /* BUCK1 VARM: 1.2V */
141 val = (1200000 - 650000) / 25000;
142 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
143 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
144 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
146 /* BUCK2 VINT: 1.1V */
147 val = (1100000 - 650000) / 25000;
148 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
149 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
150 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
153 /* BUCK3 G3D: 1.1V - OFF */
154 ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
156 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
158 val = (1100000 - 750000) / 50000;
159 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
161 /* BUCK4 CAMISP: 1.2V - OFF */
162 ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
164 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
166 val = (1200000 - 650000) / 25000;
167 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
169 /* BUCK5 VMEM: 1.2V */
170 val = (1200000 - 650000) / 25000;
171 for (i = 0; i < 8; i++)
172 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
174 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
175 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
177 /* BUCK6 CAM AF: 2.8V */
178 /* No Voltage Setting Register */
181 ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
183 /* BUCK7 VCC_SUB: 2.0V */
184 val = (2000000 - 750000) / 50000;
185 ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
187 /* LDO1 VADC: 3.3V */
188 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
189 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
191 /* LDO1 Disable active discharging */
192 ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
194 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
196 /* LDO2 VALIVE: 1.1V */
197 val = max8997_reg_ldo(1100000) | EN_LDO;
198 ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
200 /* LDO3 VUSB/MIPI: 1.1V */
201 val = max8997_reg_ldo(1100000) | DIS_LDO; /* OFF */
202 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
204 /* LDO4 VMIPI: 1.8V */
205 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
206 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
208 /* LDO5 VHSIC: 1.2V */
209 val = max8997_reg_ldo(1200000) | DIS_LDO; /* OFF */
210 ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
212 /* LDO6 VCC_1.8V_PDA: 1.8V */
213 val = max8997_reg_ldo(1800000) | EN_LDO;
214 ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
216 /* LDO7 CAM_ISP: 1.8V */
217 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
218 ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
220 /* LDO8 VDAC/VUSB: 3.3V */
221 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
222 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
224 /* LDO9 VCC_2.8V_PDA: 2.8V */
225 val = max8997_reg_ldo(2800000) | EN_LDO;
226 ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
228 /* LDO10 VPLL: 1.1V */
229 val = max8997_reg_ldo(1100000) | EN_LDO;
230 ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
232 /* LDO11 TOUCH: 2.8V */
233 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
234 ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
236 /* LDO12 VTCAM: 1.8V */
237 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
238 ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
240 /* LDO13 VCC_3.0_LCD: 3.0V */
241 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
242 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
244 /* LDO14 MOTOR: 3.0V */
245 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
246 ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
248 /* LDO15 LED_A: 2.8V */
249 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
250 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
252 /* LDO16 CAM_SENSOR: 1.8V */
253 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
254 ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
256 /* LDO17 VTF: 2.8V */
257 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
258 ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
260 /* LDO18 TOUCH_LED 3.3V */
261 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
262 ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
264 /* LDO21 VDDQ: 1.2V */
265 val = max8997_reg_ldo(1200000) | EN_LDO;
266 ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
268 /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
269 val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
270 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
271 ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
274 puts("MAX8997 PMIC setting error!\n");
280 int power_init_board(void)
283 struct power_battery *pb;
284 struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
287 * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected
288 * to logical I2C adapter 0
290 * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
291 * to logical I2C adapter 1
293 ret = pmic_init(I2C_0);
294 ret |= pmic_init_max8997();
295 ret |= power_fg_init(I2C_1);
296 ret |= power_muic_init(I2C_0);
297 ret |= power_bat_init(0);
301 p_fg = pmic_get("MAX17042_FG");
303 puts("MAX17042_FG: Not found\n");
307 p_chrg = pmic_get("MAX8997_PMIC");
309 puts("MAX8997_PMIC: Not found\n");
313 p_muic = pmic_get("MAX8997_MUIC");
315 puts("MAX8997_MUIC: Not found\n");
319 p_bat = pmic_get("BAT_TRATS");
321 puts("BAT_TRATS: Not found\n");
325 p_fg->parent = p_bat;
326 p_chrg->parent = p_bat;
327 p_muic->parent = p_bat;
329 p_bat->low_power_mode = trats_low_power_mode;
330 p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
333 chrg = p_muic->chrg->chrg_type(p_muic);
334 debug("CHARGER TYPE: %d\n", chrg);
336 if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
337 puts("No battery detected\n");
341 p_fg->fg->fg_battery_check(p_fg, p_bat);
343 if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
344 puts("CHARGE Battery !\n");
351 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
352 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
353 get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
354 get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
359 void dram_init_banksize(void)
361 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
362 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
363 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
364 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
365 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
366 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
367 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
368 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
371 static unsigned int get_hw_revision(void)
373 struct exynos4_gpio_part1 *gpio =
374 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
378 /* hw_rev[3:0] == GPE1[3:0] */
379 for (i = 0; i < 4; i++) {
380 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
381 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
386 for (i = 0; i < 4; i++)
387 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
389 debug("hwrev 0x%x\n", hwrev);
394 static void check_hw_revision(void)
398 hwrev = get_hw_revision();
403 #ifdef CONFIG_DISPLAY_BOARDINFO
406 puts("Board:\tTRATS\n");
411 #ifdef CONFIG_GENERIC_MMC
412 int board_mmc_init(bd_t *bis)
414 struct exynos4_gpio_part2 *gpio =
415 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
418 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
419 s5p_gpio_direction_output(&gpio->k0, 2, 1);
420 s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
424 * mmc0 : eMMC (8-bit buswidth)
425 * mmc2 : SD card (4-bit buswidth)
427 err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
429 debug("SDMMC0 not configured\n");
431 err = s5p_mmc_init(0, 8);
434 s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
435 s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
438 * Check the T-flash detect pin
439 * GPX3[4] T-flash detect pin
441 if (!s5p_gpio_get_value(&gpio->x3, 4)) {
442 err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
444 debug("SDMMC2 not configured\n");
446 err = s5p_mmc_init(2, 4);
453 #ifdef CONFIG_USB_GADGET
454 static int s5pc210_phy_control(int on)
458 struct pmic *p = pmic_get("MAX8997_PMIC");
466 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
468 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
469 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
471 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
472 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
474 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
475 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
477 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
478 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
479 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
480 ENSAFEOUT1, LDO_OFF);
484 puts("MAX8997 LDO setting error!\n");
491 struct s3c_plat_otg_data s5pc210_otg_data = {
492 .phy_control = s5pc210_phy_control,
493 .regs_phy = EXYNOS4_USBPHY_BASE,
494 .regs_otg = EXYNOS4_USBOTG_BASE,
495 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
496 .usb_flags = PHY0_SLEEP,
499 int board_usb_init(int index, enum usb_init_type init)
501 debug("USB_udc_probe\n");
502 return s3c_udc_probe(&s5pc210_otg_data);
505 #ifdef CONFIG_USB_CABLE_CHECK
506 int usb_cable_connected(void)
508 struct pmic *muic = pmic_get("MAX8997_MUIC");
512 return !!muic->chrg->chrg_type(muic);
517 static void pmic_reset(void)
519 struct exynos4_gpio_part2 *gpio =
520 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
522 s5p_gpio_direction_output(&gpio->x0, 7, 1);
523 s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
526 static void board_clock_init(void)
528 struct exynos4_clock *clk =
529 (struct exynos4_clock *)samsung_get_base_clock();
531 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
532 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
533 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
534 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
536 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
537 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
538 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
539 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
540 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
541 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
542 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
543 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
544 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
545 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
546 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
547 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
549 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
550 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
551 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
552 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
553 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
554 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
555 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
556 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
557 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
558 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
559 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
560 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
562 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
563 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
564 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
565 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
566 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
567 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
568 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
569 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
570 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
571 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
572 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
573 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
576 static void board_power_init(void)
578 struct exynos4_power *pwr =
579 (struct exynos4_power *)samsung_get_base_power();
582 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
585 writel(0, (unsigned int)&pwr->cam_configuration);
586 writel(0, (unsigned int)&pwr->tv_configuration);
587 writel(0, (unsigned int)&pwr->mfc_configuration);
588 writel(0, (unsigned int)&pwr->g3d_configuration);
589 writel(0, (unsigned int)&pwr->lcd1_configuration);
590 writel(0, (unsigned int)&pwr->gps_configuration);
591 writel(0, (unsigned int)&pwr->gps_alive_configuration);
593 /* It is necessary to power down core 1 */
594 /* to successfully boot CPU1 in kernel */
595 writel(0, (unsigned int)&pwr->arm_core1_configuration);
598 static void board_uart_init(void)
600 struct exynos4_gpio_part1 *gpio1 =
601 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
602 struct exynos4_gpio_part2 *gpio2 =
603 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
608 * GPA1CON[0] = UART_2_RXD(2)
609 * GPA1CON[1] = UART_2_TXD(2)
610 * GPA1CON[2] = I2C_3_SDA (3)
611 * GPA1CON[3] = I2C_3_SCL (3)
614 for (i = 0; i < 4; i++) {
615 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
616 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
619 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
620 s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
621 s5p_gpio_direction_output(&gpio2->y4, 7, 1);
624 int board_early_init_f(void)
635 void exynos_reset_lcd(void)
637 struct exynos4_gpio_part2 *gpio2 =
638 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
640 s5p_gpio_direction_output(&gpio2->y4, 5, 1);
642 s5p_gpio_direction_output(&gpio2->y4, 5, 0);
644 s5p_gpio_direction_output(&gpio2->y4, 5, 1);
647 static int lcd_power(void)
650 struct pmic *p = pmic_get("MAX8997_PMIC");
657 /* LDO15 voltage: 2.2v */
658 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
659 /* LDO13 voltage: 3.0v */
660 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
663 puts("MAX8997 LDO setting error!\n");
670 static struct mipi_dsim_config dsim_config = {
671 .e_interface = DSIM_VIDEO,
672 .e_virtual_ch = DSIM_VIRTUAL_CH_0,
673 .e_pixel_format = DSIM_24BPP_888,
674 .e_burst_mode = DSIM_BURST_SYNC_EVENT,
675 .e_no_data_lane = DSIM_DATA_LANE_4,
676 .e_byte_clk = DSIM_PLL_OUT_DIV8,
683 /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
684 .pll_stable_time = 500,
686 /* escape clk : 10MHz */
687 .esc_clk = 20 * 1000000,
689 /* stop state holding counter after bta change count 0 ~ 0xfff */
690 .stop_holding_cnt = 0x7ff,
691 /* bta timeout 0 ~ 0xff */
693 /* lp rx timeout 0 ~ 0xffff */
694 .rx_timeout = 0xffff,
697 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
698 .lcd_panel_info = NULL,
699 .dsim_config = &dsim_config,
702 static struct mipi_dsim_lcd_device mipi_lcd_device = {
706 .platform_data = (void *)&s6e8ax0_platform_data,
709 static int mipi_power(void)
712 struct pmic *p = pmic_get("MAX8997_PMIC");
719 /* LDO3 voltage: 1.1v */
720 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
721 /* LDO4 voltage: 1.8v */
722 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
725 puts("MAX8997 LDO setting error!\n");
732 vidinfo_t panel_info = {
738 .vl_clkp = CONFIG_SYS_HIGH,
739 .vl_hsp = CONFIG_SYS_LOW,
740 .vl_vsp = CONFIG_SYS_LOW,
741 .vl_dp = CONFIG_SYS_LOW,
742 .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */
744 /* s6e8ax0 Panel infomation */
752 .vl_cmd_allow_len = 0xf,
755 .dual_lcd_enabled = 0,
760 .interface_mode = FIMD_RGB_INTERFACE,
764 void init_panel_info(vidinfo_t *vid)
767 vid->resolution = HD_RESOLUTION,
768 vid->rgb_mode = MODE_RGB_P,
771 get_tizen_logo_info(vid);
773 mipi_lcd_device.reverse_panel = 1;
775 strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
776 s6e8ax0_platform_data.lcd_power = lcd_power;
777 s6e8ax0_platform_data.mipi_power = mipi_power;
778 s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
779 s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
780 exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
782 exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
784 setenv("lcdinfo", "lcd=s6e8ax0");