board/samsung/trats/trats.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics
   3  * Heungjun Kim <riverful.kim@samsung.com>
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  * Donghwa Lee <dh09.lee@samsung.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <lcd.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/cpu.h>
  30 #include <asm/arch/gpio.h>
  31 #include <asm/arch/mmc.h>
  32 #include <asm/arch/clock.h>
  33 #include <asm/arch/clk.h>
  34 #include <asm/arch/mipi_dsim.h>
  35 #include <asm/arch/watchdog.h>
  36 #include <asm/arch/power.h>
  37 #include <power/pmic.h>
  38 #include <usb/s3c_udc.h>
  39 #include <power/max8997_pmic.h>
  40 #include <libtizen.h>
  41
  42 #include "setup.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 unsigned int board_rev;
  47
  48 #ifdef CONFIG_REVISION_TAG
  49 u32 get_board_rev(void)
  50 {
  51         return board_rev;
  52 }
  53 #endif
  54
  55 static void check_hw_revision(void);
  56
  57 static int hwrevision(int rev)
  58 {
  59         return (board_rev & 0xf) == rev;
  60 }
  61
  62 struct s3c_plat_otg_data s5pc210_otg_data;
  63
  64 int board_init(void)
  65 {
  66         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  67
  68         check_hw_revision();
  69         printf("HW Revision:\t0x%x\n", board_rev);
  70
  71         return 0;
  72 }
  73
  74 void i2c_init_board(void)
  75 {
  76         struct exynos4_gpio_part1 *gpio1 =
  77                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
  78         struct exynos4_gpio_part2 *gpio2 =
  79                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
  80
  81         /* I2C_5 -> PMIC */
  82         s5p_gpio_direction_output(&gpio1->b, 7, 1);
  83         s5p_gpio_direction_output(&gpio1->b, 6, 1);
  84         /* I2C_9 -> FG */
  85         s5p_gpio_direction_output(&gpio2->y4, 0, 1);
  86         s5p_gpio_direction_output(&gpio2->y4, 1, 1);
  87 }
  88
  89 static int pmic_init_max8997(void)
  90 {
  91         struct pmic *p = pmic_get("MAX8997_PMIC");
  92         int i = 0, ret = 0;
  93         u32 val;
  94
  95         if (pmic_probe(p))
  96                 return -1;
  97
  98         /* BUCK1 VARM: 1.2V */
  99         val = (1200000 - 650000) / 25000;
 100         ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
 101         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 102         ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
 103
 104         /* BUCK2 VINT: 1.1V */
 105         val = (1100000 - 650000) / 25000;
 106         ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
 107         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 108         ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
 109
 110
 111         /* BUCK3 G3D: 1.1V - OFF */
 112         ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
 113         val &= ~ENBUCK;
 114         ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
 115
 116         val = (1100000 - 750000) / 50000;
 117         ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
 118
 119         /* BUCK4 CAMISP: 1.2V - OFF */
 120         ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
 121         val &= ~ENBUCK;
 122         ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
 123
 124         val = (1200000 - 650000) / 25000;
 125         ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
 126
 127         /* BUCK5 VMEM: 1.2V */
 128         val = (1200000 - 650000) / 25000;
 129         for (i = 0; i < 8; i++)
 130                 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
 131
 132         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 133         ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
 134
 135         /* BUCK6 CAM AF: 2.8V */
 136         /* No Voltage Setting Register */
 137         /* GNSLCT 3.0X */
 138         val = GNSLCT;
 139         ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
 140
 141         /* BUCK7 VCC_SUB: 2.0V */
 142         val = (2000000 - 750000) / 50000;
 143         ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
 144
 145         /* LDO1 VADC: 3.3V */
 146         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 147         ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
 148
 149         /* LDO1 Disable active discharging */
 150         ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
 151         val &= ~LDO_ADE;
 152         ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
 153
 154         /* LDO2 VALIVE: 1.1V */
 155         val = max8997_reg_ldo(1100000) | EN_LDO;
 156         ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
 157
 158         /* LDO3 VUSB/MIPI: 1.1V */
 159         val = max8997_reg_ldo(1100000) | DIS_LDO;       /* OFF */
 160         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
 161
 162         /* LDO4 VMIPI: 1.8V */
 163         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 164         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
 165
 166         /* LDO5 VHSIC: 1.2V */
 167         val = max8997_reg_ldo(1200000) | DIS_LDO;       /* OFF */
 168         ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
 169
 170         /* LDO6 VCC_1.8V_PDA: 1.8V */
 171         val = max8997_reg_ldo(1800000) | EN_LDO;
 172         ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
 173
 174         /* LDO7 CAM_ISP: 1.8V */
 175         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 176         ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
 177
 178         /* LDO8 VDAC/VUSB: 3.3V */
 179         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 180         ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
 181
 182         /* LDO9 VCC_2.8V_PDA: 2.8V */
 183         val = max8997_reg_ldo(2800000) | EN_LDO;
 184         ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
 185
 186         /* LDO10 VPLL: 1.1V */
 187         val = max8997_reg_ldo(1100000) | EN_LDO;
 188         ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
 189
 190         /* LDO11 TOUCH: 2.8V */
 191         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 192         ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
 193
 194         /* LDO12 VTCAM: 1.8V */
 195         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 196         ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
 197
 198         /* LDO13 VCC_3.0_LCD: 3.0V */
 199         val = max8997_reg_ldo(3000000) | DIS_LDO;       /* OFF */
 200         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
 201
 202         /* LDO14 MOTOR: 3.0V */
 203         val = max8997_reg_ldo(3000000) | DIS_LDO;       /* OFF */
 204         ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
 205
 206         /* LDO15 LED_A: 2.8V */
 207         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 208         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
 209
 210         /* LDO16 CAM_SENSOR: 1.8V */
 211         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 212         ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
 213
 214         /* LDO17 VTF: 2.8V */
 215         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 216         ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
 217
 218         /* LDO18 TOUCH_LED 3.3V */
 219         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 220         ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
 221
 222         /* LDO21 VDDQ: 1.2V */
 223         val = max8997_reg_ldo(1200000) | EN_LDO;
 224         ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
 225
 226         /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
 227         val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
 228                 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
 229         ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
 230
 231         if (ret) {
 232                 puts("MAX8997 PMIC setting error!\n");
 233                 return -1;
 234         }
 235         return 0;
 236 }
 237
 238 int power_init_board(void)
 239 {
 240         int ret;
 241
 242         ret = pmic_init(I2C_5);
 243         ret |= pmic_init_max8997();
 244
 245         if (ret)
 246                 return ret;
 247
 248         return 0;
 249 }
 250
 251 int dram_init(void)
 252 {
 253         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
 254                 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
 255
 256         return 0;
 257 }
 258
 259 void dram_init_banksize(void)
 260 {
 261         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 262         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 263         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 264         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 265 }
 266
 267 static unsigned int get_hw_revision(void)
 268 {
 269         struct exynos4_gpio_part1 *gpio =
 270                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 271         int hwrev = 0;
 272         int i;
 273
 274         /* hw_rev[3:0] == GPE1[3:0] */
 275         for (i = 0; i < 4; i++) {
 276                 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
 277                 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
 278         }
 279
 280         udelay(1);
 281
 282         for (i = 0; i < 4; i++)
 283                 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
 284
 285         debug("hwrev 0x%x\n", hwrev);
 286
 287         return hwrev;
 288 }
 289
 290 static void check_hw_revision(void)
 291 {
 292         int hwrev;
 293
 294         hwrev = get_hw_revision();
 295
 296         board_rev |= hwrev;
 297 }
 298
 299 #ifdef CONFIG_DISPLAY_BOARDINFO
 300 int checkboard(void)
 301 {
 302         puts("Board:\tTRATS\n");
 303         return 0;
 304 }
 305 #endif
 306
 307 #ifdef CONFIG_GENERIC_MMC
 308 int board_mmc_init(bd_t *bis)
 309 {
 310         struct exynos4_gpio_part2 *gpio =
 311                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 312         int i, err;
 313
 314         /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
 315         s5p_gpio_direction_output(&gpio->k0, 2, 1);
 316         s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
 317
 318         /*
 319          * eMMC GPIO:
 320          * SDR 8-bit@48MHz at MMC0
 321          * GPK0[0]      SD_0_CLK(2)
 322          * GPK0[1]      SD_0_CMD(2)
 323          * GPK0[2]      SD_0_CDn        -> Not used
 324          * GPK0[3:6]    SD_0_DATA[0:3](2)
 325          * GPK1[3:6]    SD_0_DATA[0:3](3)
 326          *
 327          * DDR 4-bit@26MHz at MMC4
 328          * GPK0[0]      SD_4_CLK(3)
 329          * GPK0[1]      SD_4_CMD(3)
 330          * GPK0[2]      SD_4_CDn        -> Not used
 331          * GPK0[3:6]    SD_4_DATA[0:3](3)
 332          * GPK1[3:6]    SD_4_DATA[4:7](4)
 333          */
 334         for (i = 0; i < 7; i++) {
 335                 if (i == 2)
 336                         continue;
 337                 /* GPK0[0:6] special function 2 */
 338                 s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
 339                 /* GPK0[0:6] pull disable */
 340                 s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
 341                 /* GPK0[0:6] drv 4x */
 342                 s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
 343         }
 344
 345         for (i = 3; i < 7; i++) {
 346                 /* GPK1[3:6] special function 3 */
 347                 s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
 348                 /* GPK1[3:6] pull disable */
 349                 s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
 350                 /* GPK1[3:6] drv 4x */
 351                 s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
 352         }
 353
 354         /*
 355          * MMC device init
 356          * mmc0  : eMMC (8-bit buswidth)
 357          * mmc2  : SD card (4-bit buswidth)
 358          */
 359         err = s5p_mmc_init(0, 8);
 360
 361         /* T-flash detect */
 362         s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
 363         s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
 364
 365         /*
 366          * Check the T-flash  detect pin
 367          * GPX3[4] T-flash detect pin
 368          */
 369         if (!s5p_gpio_get_value(&gpio->x3, 4)) {
 370                 /*
 371                  * SD card GPIO:
 372                  * GPK2[0]      SD_2_CLK(2)
 373                  * GPK2[1]      SD_2_CMD(2)
 374                  * GPK2[2]      SD_2_CDn        -> Not used
 375                  * GPK2[3:6]    SD_2_DATA[0:3](2)
 376                  */
 377                 for (i = 0; i < 7; i++) {
 378                         if (i == 2)
 379                                 continue;
 380                         /* GPK2[0:6] special function 2 */
 381                         s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
 382                         /* GPK2[0:6] pull disable */
 383                         s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
 384                         /* GPK2[0:6] drv 4x */
 385                         s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
 386                 }
 387                 err = s5p_mmc_init(2, 4);
 388         }
 389
 390         return err;
 391 }
 392 #endif
 393
 394 #ifdef CONFIG_USB_GADGET
 395 static int s5pc210_phy_control(int on)
 396 {
 397         int ret = 0;
 398         u32 val = 0;
 399         struct pmic *p = pmic_get("MAX8997_PMIC");
 400         if (!p)
 401                 return -ENODEV;
 402
 403         if (pmic_probe(p))
 404                 return -1;
 405
 406         if (on) {
 407                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 408                                       ENSAFEOUT1, LDO_ON);
 409                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 410                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
 411
 412                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 413                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
 414         } else {
 415                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 416                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
 417
 418                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 419                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
 420                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 421                                       ENSAFEOUT1, LDO_OFF);
 422         }
 423
 424         if (ret) {
 425                 puts("MAX8997 LDO setting error!\n");
 426                 return -1;
 427         }
 428
 429         return 0;
 430 }
 431
 432 struct s3c_plat_otg_data s5pc210_otg_data = {
 433         .phy_control    = s5pc210_phy_control,
 434         .regs_phy       = EXYNOS4_USBPHY_BASE,
 435         .regs_otg       = EXYNOS4_USBOTG_BASE,
 436         .usb_phy_ctrl   = EXYNOS4_USBPHY_CONTROL,
 437         .usb_flags      = PHY0_SLEEP,
 438 };
 439
 440 void board_usb_init(void)
 441 {
 442         debug("USB_udc_probe\n");
 443         s3c_udc_probe(&s5pc210_otg_data);
 444 }
 445 #endif
 446
 447 static void pmic_reset(void)
 448 {
 449         struct exynos4_gpio_part2 *gpio =
 450                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 451
 452         s5p_gpio_direction_output(&gpio->x0, 7, 1);
 453         s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
 454 }
 455
 456 static void board_clock_init(void)
 457 {
 458         struct exynos4_clock *clk =
 459                 (struct exynos4_clock *)samsung_get_base_clock();
 460
 461         writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
 462         writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
 463         writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
 464         writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
 465
 466         writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
 467         writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
 468         writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
 469         writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
 470         writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
 471         writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
 472         writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
 473         writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
 474         writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
 475         writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
 476         writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
 477         writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
 478
 479         writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
 480         writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
 481         writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
 482         writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
 483         writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
 484         writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
 485         writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
 486         writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
 487         writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
 488         writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
 489         writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
 490         writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
 491
 492         writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
 493         writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
 494         writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
 495         writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
 496         writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
 497         writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
 498         writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
 499         writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
 500         writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
 501         writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
 502         writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
 503         writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
 504 }
 505
 506 static void board_power_init(void)
 507 {
 508         struct exynos4_power *pwr =
 509                 (struct exynos4_power *)samsung_get_base_power();
 510
 511         /* PS HOLD */
 512         writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
 513
 514         /* Set power down */
 515         writel(0, (unsigned int)&pwr->cam_configuration);
 516         writel(0, (unsigned int)&pwr->tv_configuration);
 517         writel(0, (unsigned int)&pwr->mfc_configuration);
 518         writel(0, (unsigned int)&pwr->g3d_configuration);
 519         writel(0, (unsigned int)&pwr->lcd1_configuration);
 520         writel(0, (unsigned int)&pwr->gps_configuration);
 521         writel(0, (unsigned int)&pwr->gps_alive_configuration);
 522 }
 523
 524 static void board_uart_init(void)
 525 {
 526         struct exynos4_gpio_part1 *gpio1 =
 527                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 528         struct exynos4_gpio_part2 *gpio2 =
 529                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 530         int i;
 531
 532         /*
 533          * UART2 GPIOs
 534          * GPA1CON[0] = UART_2_RXD(2)
 535          * GPA1CON[1] = UART_2_TXD(2)
 536          * GPA1CON[2] = I2C_3_SDA (3)
 537          * GPA1CON[3] = I2C_3_SCL (3)
 538          */
 539
 540         for (i = 0; i < 4; i++) {
 541                 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
 542                 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
 543         }
 544
 545         /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
 546         s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
 547         s5p_gpio_direction_output(&gpio2->y4, 7, 1);
 548 }
 549
 550 int board_early_init_f(void)
 551 {
 552         wdt_stop();
 553         pmic_reset();
 554         board_clock_init();
 555         board_uart_init();
 556         board_power_init();
 557
 558         return 0;
 559 }
 560
 561 static void lcd_reset(void)
 562 {
 563         struct exynos4_gpio_part2 *gpio2 =
 564                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 565
 566         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 567         udelay(10000);
 568         s5p_gpio_direction_output(&gpio2->y4, 5, 0);
 569         udelay(10000);
 570         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 571 }
 572
 573 static int lcd_power(void)
 574 {
 575         int ret = 0;
 576         struct pmic *p = pmic_get("MAX8997_PMIC");
 577         if (!p)
 578                 return -ENODEV;
 579
 580         if (pmic_probe(p))
 581                 return 0;
 582
 583         /* LDO15 voltage: 2.2v */
 584         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
 585         /* LDO13 voltage: 3.0v */
 586         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
 587
 588         if (ret) {
 589                 puts("MAX8997 LDO setting error!\n");
 590                 return -1;
 591         }
 592
 593         return 0;
 594 }
 595
 596 static struct mipi_dsim_config dsim_config = {
 597         .e_interface            = DSIM_VIDEO,
 598         .e_virtual_ch           = DSIM_VIRTUAL_CH_0,
 599         .e_pixel_format         = DSIM_24BPP_888,
 600         .e_burst_mode           = DSIM_BURST_SYNC_EVENT,
 601         .e_no_data_lane         = DSIM_DATA_LANE_4,
 602         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 603         .hfp                    = 1,
 604
 605         .p                      = 3,
 606         .m                      = 120,
 607         .s                      = 1,
 608
 609         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 610         .pll_stable_time        = 500,
 611
 612         /* escape clk : 10MHz */
 613         .esc_clk                = 20 * 1000000,
 614
 615         /* stop state holding counter after bta change count 0 ~ 0xfff */
 616         .stop_holding_cnt       = 0x7ff,
 617         /* bta timeout 0 ~ 0xff */
 618         .bta_timeout            = 0xff,
 619         /* lp rx timeout 0 ~ 0xffff */
 620         .rx_timeout             = 0xffff,
 621 };
 622
 623 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
 624         .lcd_panel_info = NULL,
 625         .dsim_config = &dsim_config,
 626 };
 627
 628 static struct mipi_dsim_lcd_device mipi_lcd_device = {
 629         .name   = "s6e8ax0",
 630         .id     = -1,
 631         .bus_id = 0,
 632         .platform_data  = (void *)&s6e8ax0_platform_data,
 633 };
 634
 635 static int mipi_power(void)
 636 {
 637         int ret = 0;
 638         struct pmic *p = pmic_get("MAX8997_PMIC");
 639         if (!p)
 640                 return -ENODEV;
 641
 642         if (pmic_probe(p))
 643                 return 0;
 644
 645         /* LDO3 voltage: 1.1v */
 646         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
 647         /* LDO4 voltage: 1.8v */
 648         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
 649
 650         if (ret) {
 651                 puts("MAX8997 LDO setting error!\n");
 652                 return -1;
 653         }
 654
 655         return 0;
 656 }
 657
 658 vidinfo_t panel_info = {
 659         .vl_freq        = 60,
 660         .vl_col         = 720,
 661         .vl_row         = 1280,
 662         .vl_width       = 720,
 663         .vl_height      = 1280,
 664         .vl_clkp        = CONFIG_SYS_HIGH,
 665         .vl_hsp         = CONFIG_SYS_LOW,
 666         .vl_vsp         = CONFIG_SYS_LOW,
 667         .vl_dp          = CONFIG_SYS_LOW,
 668         .vl_bpix        = 5,    /* Bits per pixel, 2^5 = 32 */
 669
 670         /* s6e8ax0 Panel infomation */
 671         .vl_hspw        = 5,
 672         .vl_hbpd        = 10,
 673         .vl_hfpd        = 10,
 674
 675         .vl_vspw        = 2,
 676         .vl_vbpd        = 1,
 677         .vl_vfpd        = 13,
 678         .vl_cmd_allow_len = 0xf,
 679
 680         .win_id         = 3,
 681         .cfg_gpio       = NULL,
 682         .backlight_on   = NULL,
 683         .lcd_power_on   = NULL, /* lcd_power_on in mipi dsi driver */
 684         .reset_lcd      = lcd_reset,
 685         .dual_lcd_enabled = 0,
 686
 687         .init_delay     = 0,
 688         .power_on_delay = 0,
 689         .reset_delay    = 0,
 690         .interface_mode = FIMD_RGB_INTERFACE,
 691         .mipi_enabled   = 1,
 692 };
 693
 694 void init_panel_info(vidinfo_t *vid)
 695 {
 696         vid->logo_on    = 1,
 697         vid->resolution = HD_RESOLUTION,
 698         vid->rgb_mode   = MODE_RGB_P,
 699
 700 #ifdef CONFIG_TIZEN
 701         get_tizen_logo_info(vid);
 702 #endif
 703
 704         if (hwrevision(2))
 705                 mipi_lcd_device.reverse_panel = 1;
 706
 707         strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
 708         s6e8ax0_platform_data.lcd_power = lcd_power;
 709         s6e8ax0_platform_data.mipi_power = mipi_power;
 710         s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
 711         s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
 712         exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
 713         s6e8ax0_init();
 714         exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
 715
 716         setenv("lcdinfo", "lcd=s6e8ax0");
 717 }