board/samsung/trats/trats.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics
   3  * Heungjun Kim <riverful.kim@samsung.com>
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  * Donghwa Lee <dh09.lee@samsung.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <lcd.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/cpu.h>
  30 #include <asm/arch/gpio.h>
  31 #include <asm/arch/mmc.h>
  32 #include <asm/arch/clock.h>
  33 #include <asm/arch/clk.h>
  34 #include <asm/arch/mipi_dsim.h>
  35 #include <asm/arch/watchdog.h>
  36 #include <asm/arch/power.h>
  37 #include <power/pmic.h>
  38 #include <usb/s3c_udc.h>
  39 #include <power/max8997_pmic.h>
  40 #include <libtizen.h>
  41 #include <power/max8997_muic.h>
  42
  43 #include "setup.h"
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 unsigned int board_rev;
  48
  49 #ifdef CONFIG_REVISION_TAG
  50 u32 get_board_rev(void)
  51 {
  52         return board_rev;
  53 }
  54 #endif
  55
  56 static void check_hw_revision(void);
  57
  58 static int hwrevision(int rev)
  59 {
  60         return (board_rev & 0xf) == rev;
  61 }
  62
  63 struct s3c_plat_otg_data s5pc210_otg_data;
  64
  65 int board_init(void)
  66 {
  67         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  68
  69         check_hw_revision();
  70         printf("HW Revision:\t0x%x\n", board_rev);
  71
  72         return 0;
  73 }
  74
  75 void i2c_init_board(void)
  76 {
  77         struct exynos4_gpio_part1 *gpio1 =
  78                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
  79         struct exynos4_gpio_part2 *gpio2 =
  80                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
  81
  82         /* I2C_5 -> PMIC */
  83         s5p_gpio_direction_output(&gpio1->b, 7, 1);
  84         s5p_gpio_direction_output(&gpio1->b, 6, 1);
  85         /* I2C_9 -> FG */
  86         s5p_gpio_direction_output(&gpio2->y4, 0, 1);
  87         s5p_gpio_direction_output(&gpio2->y4, 1, 1);
  88 }
  89
  90 static int pmic_init_max8997(void)
  91 {
  92         struct pmic *p = pmic_get("MAX8997_PMIC");
  93         int i = 0, ret = 0;
  94         u32 val;
  95
  96         if (pmic_probe(p))
  97                 return -1;
  98
  99         /* BUCK1 VARM: 1.2V */
 100         val = (1200000 - 650000) / 25000;
 101         ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
 102         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 103         ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
 104
 105         /* BUCK2 VINT: 1.1V */
 106         val = (1100000 - 650000) / 25000;
 107         ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
 108         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 109         ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
 110
 111
 112         /* BUCK3 G3D: 1.1V - OFF */
 113         ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
 114         val &= ~ENBUCK;
 115         ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
 116
 117         val = (1100000 - 750000) / 50000;
 118         ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
 119
 120         /* BUCK4 CAMISP: 1.2V - OFF */
 121         ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
 122         val &= ~ENBUCK;
 123         ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
 124
 125         val = (1200000 - 650000) / 25000;
 126         ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
 127
 128         /* BUCK5 VMEM: 1.2V */
 129         val = (1200000 - 650000) / 25000;
 130         for (i = 0; i < 8; i++)
 131                 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
 132
 133         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 134         ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
 135
 136         /* BUCK6 CAM AF: 2.8V */
 137         /* No Voltage Setting Register */
 138         /* GNSLCT 3.0X */
 139         val = GNSLCT;
 140         ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
 141
 142         /* BUCK7 VCC_SUB: 2.0V */
 143         val = (2000000 - 750000) / 50000;
 144         ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
 145
 146         /* LDO1 VADC: 3.3V */
 147         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 148         ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
 149
 150         /* LDO1 Disable active discharging */
 151         ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
 152         val &= ~LDO_ADE;
 153         ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
 154
 155         /* LDO2 VALIVE: 1.1V */
 156         val = max8997_reg_ldo(1100000) | EN_LDO;
 157         ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
 158
 159         /* LDO3 VUSB/MIPI: 1.1V */
 160         val = max8997_reg_ldo(1100000) | DIS_LDO;       /* OFF */
 161         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
 162
 163         /* LDO4 VMIPI: 1.8V */
 164         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 165         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
 166
 167         /* LDO5 VHSIC: 1.2V */
 168         val = max8997_reg_ldo(1200000) | DIS_LDO;       /* OFF */
 169         ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
 170
 171         /* LDO6 VCC_1.8V_PDA: 1.8V */
 172         val = max8997_reg_ldo(1800000) | EN_LDO;
 173         ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
 174
 175         /* LDO7 CAM_ISP: 1.8V */
 176         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 177         ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
 178
 179         /* LDO8 VDAC/VUSB: 3.3V */
 180         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 181         ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
 182
 183         /* LDO9 VCC_2.8V_PDA: 2.8V */
 184         val = max8997_reg_ldo(2800000) | EN_LDO;
 185         ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
 186
 187         /* LDO10 VPLL: 1.1V */
 188         val = max8997_reg_ldo(1100000) | EN_LDO;
 189         ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
 190
 191         /* LDO11 TOUCH: 2.8V */
 192         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 193         ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
 194
 195         /* LDO12 VTCAM: 1.8V */
 196         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 197         ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
 198
 199         /* LDO13 VCC_3.0_LCD: 3.0V */
 200         val = max8997_reg_ldo(3000000) | DIS_LDO;       /* OFF */
 201         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
 202
 203         /* LDO14 MOTOR: 3.0V */
 204         val = max8997_reg_ldo(3000000) | DIS_LDO;       /* OFF */
 205         ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
 206
 207         /* LDO15 LED_A: 2.8V */
 208         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 209         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
 210
 211         /* LDO16 CAM_SENSOR: 1.8V */
 212         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 213         ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
 214
 215         /* LDO17 VTF: 2.8V */
 216         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 217         ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
 218
 219         /* LDO18 TOUCH_LED 3.3V */
 220         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 221         ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
 222
 223         /* LDO21 VDDQ: 1.2V */
 224         val = max8997_reg_ldo(1200000) | EN_LDO;
 225         ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
 226
 227         /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
 228         val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
 229                 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
 230         ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
 231
 232         if (ret) {
 233                 puts("MAX8997 PMIC setting error!\n");
 234                 return -1;
 235         }
 236         return 0;
 237 }
 238
 239 int power_init_board(void)
 240 {
 241         int ret;
 242
 243         ret = pmic_init(I2C_5);
 244         ret |= pmic_init_max8997();
 245         ret |= power_muic_init(I2C_5);
 246         if (ret)
 247                 return ret;
 248
 249         return 0;
 250 }
 251
 252 int dram_init(void)
 253 {
 254         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
 255                 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
 256
 257         return 0;
 258 }
 259
 260 void dram_init_banksize(void)
 261 {
 262         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 263         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 264         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 265         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 266 }
 267
 268 static unsigned int get_hw_revision(void)
 269 {
 270         struct exynos4_gpio_part1 *gpio =
 271                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 272         int hwrev = 0;
 273         int i;
 274
 275         /* hw_rev[3:0] == GPE1[3:0] */
 276         for (i = 0; i < 4; i++) {
 277                 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
 278                 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
 279         }
 280
 281         udelay(1);
 282
 283         for (i = 0; i < 4; i++)
 284                 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
 285
 286         debug("hwrev 0x%x\n", hwrev);
 287
 288         return hwrev;
 289 }
 290
 291 static void check_hw_revision(void)
 292 {
 293         int hwrev;
 294
 295         hwrev = get_hw_revision();
 296
 297         board_rev |= hwrev;
 298 }
 299
 300 #ifdef CONFIG_DISPLAY_BOARDINFO
 301 int checkboard(void)
 302 {
 303         puts("Board:\tTRATS\n");
 304         return 0;
 305 }
 306 #endif
 307
 308 #ifdef CONFIG_GENERIC_MMC
 309 int board_mmc_init(bd_t *bis)
 310 {
 311         struct exynos4_gpio_part2 *gpio =
 312                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 313         int i, err;
 314
 315         /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
 316         s5p_gpio_direction_output(&gpio->k0, 2, 1);
 317         s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
 318
 319         /*
 320          * eMMC GPIO:
 321          * SDR 8-bit@48MHz at MMC0
 322          * GPK0[0]      SD_0_CLK(2)
 323          * GPK0[1]      SD_0_CMD(2)
 324          * GPK0[2]      SD_0_CDn        -> Not used
 325          * GPK0[3:6]    SD_0_DATA[0:3](2)
 326          * GPK1[3:6]    SD_0_DATA[0:3](3)
 327          *
 328          * DDR 4-bit@26MHz at MMC4
 329          * GPK0[0]      SD_4_CLK(3)
 330          * GPK0[1]      SD_4_CMD(3)
 331          * GPK0[2]      SD_4_CDn        -> Not used
 332          * GPK0[3:6]    SD_4_DATA[0:3](3)
 333          * GPK1[3:6]    SD_4_DATA[4:7](4)
 334          */
 335         for (i = 0; i < 7; i++) {
 336                 if (i == 2)
 337                         continue;
 338                 /* GPK0[0:6] special function 2 */
 339                 s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
 340                 /* GPK0[0:6] pull disable */
 341                 s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
 342                 /* GPK0[0:6] drv 4x */
 343                 s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
 344         }
 345
 346         for (i = 3; i < 7; i++) {
 347                 /* GPK1[3:6] special function 3 */
 348                 s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
 349                 /* GPK1[3:6] pull disable */
 350                 s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
 351                 /* GPK1[3:6] drv 4x */
 352                 s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
 353         }
 354
 355         /*
 356          * MMC device init
 357          * mmc0  : eMMC (8-bit buswidth)
 358          * mmc2  : SD card (4-bit buswidth)
 359          */
 360         err = s5p_mmc_init(0, 8);
 361
 362         /* T-flash detect */
 363         s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
 364         s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
 365
 366         /*
 367          * Check the T-flash  detect pin
 368          * GPX3[4] T-flash detect pin
 369          */
 370         if (!s5p_gpio_get_value(&gpio->x3, 4)) {
 371                 /*
 372                  * SD card GPIO:
 373                  * GPK2[0]      SD_2_CLK(2)
 374                  * GPK2[1]      SD_2_CMD(2)
 375                  * GPK2[2]      SD_2_CDn        -> Not used
 376                  * GPK2[3:6]    SD_2_DATA[0:3](2)
 377                  */
 378                 for (i = 0; i < 7; i++) {
 379                         if (i == 2)
 380                                 continue;
 381                         /* GPK2[0:6] special function 2 */
 382                         s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
 383                         /* GPK2[0:6] pull disable */
 384                         s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
 385                         /* GPK2[0:6] drv 4x */
 386                         s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
 387                 }
 388                 err = s5p_mmc_init(2, 4);
 389         }
 390
 391         return err;
 392 }
 393 #endif
 394
 395 #ifdef CONFIG_USB_GADGET
 396 static int s5pc210_phy_control(int on)
 397 {
 398         int ret = 0;
 399         u32 val = 0;
 400         struct pmic *p = pmic_get("MAX8997_PMIC");
 401         if (!p)
 402                 return -ENODEV;
 403
 404         if (pmic_probe(p))
 405                 return -1;
 406
 407         if (on) {
 408                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 409                                       ENSAFEOUT1, LDO_ON);
 410                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 411                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
 412
 413                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 414                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
 415         } else {
 416                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 417                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
 418
 419                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 420                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
 421                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 422                                       ENSAFEOUT1, LDO_OFF);
 423         }
 424
 425         if (ret) {
 426                 puts("MAX8997 LDO setting error!\n");
 427                 return -1;
 428         }
 429
 430         return 0;
 431 }
 432
 433 struct s3c_plat_otg_data s5pc210_otg_data = {
 434         .phy_control    = s5pc210_phy_control,
 435         .regs_phy       = EXYNOS4_USBPHY_BASE,
 436         .regs_otg       = EXYNOS4_USBOTG_BASE,
 437         .usb_phy_ctrl   = EXYNOS4_USBPHY_CONTROL,
 438         .usb_flags      = PHY0_SLEEP,
 439 };
 440
 441 void board_usb_init(void)
 442 {
 443         debug("USB_udc_probe\n");
 444         s3c_udc_probe(&s5pc210_otg_data);
 445 }
 446 #endif
 447
 448 static void pmic_reset(void)
 449 {
 450         struct exynos4_gpio_part2 *gpio =
 451                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 452
 453         s5p_gpio_direction_output(&gpio->x0, 7, 1);
 454         s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
 455 }
 456
 457 static void board_clock_init(void)
 458 {
 459         struct exynos4_clock *clk =
 460                 (struct exynos4_clock *)samsung_get_base_clock();
 461
 462         writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
 463         writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
 464         writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
 465         writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
 466
 467         writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
 468         writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
 469         writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
 470         writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
 471         writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
 472         writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
 473         writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
 474         writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
 475         writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
 476         writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
 477         writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
 478         writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
 479
 480         writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
 481         writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
 482         writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
 483         writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
 484         writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
 485         writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
 486         writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
 487         writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
 488         writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
 489         writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
 490         writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
 491         writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
 492
 493         writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
 494         writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
 495         writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
 496         writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
 497         writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
 498         writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
 499         writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
 500         writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
 501         writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
 502         writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
 503         writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
 504         writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
 505 }
 506
 507 static void board_power_init(void)
 508 {
 509         struct exynos4_power *pwr =
 510                 (struct exynos4_power *)samsung_get_base_power();
 511
 512         /* PS HOLD */
 513         writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
 514
 515         /* Set power down */
 516         writel(0, (unsigned int)&pwr->cam_configuration);
 517         writel(0, (unsigned int)&pwr->tv_configuration);
 518         writel(0, (unsigned int)&pwr->mfc_configuration);
 519         writel(0, (unsigned int)&pwr->g3d_configuration);
 520         writel(0, (unsigned int)&pwr->lcd1_configuration);
 521         writel(0, (unsigned int)&pwr->gps_configuration);
 522         writel(0, (unsigned int)&pwr->gps_alive_configuration);
 523 }
 524
 525 static void board_uart_init(void)
 526 {
 527         struct exynos4_gpio_part1 *gpio1 =
 528                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 529         struct exynos4_gpio_part2 *gpio2 =
 530                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 531         int i;
 532
 533         /*
 534          * UART2 GPIOs
 535          * GPA1CON[0] = UART_2_RXD(2)
 536          * GPA1CON[1] = UART_2_TXD(2)
 537          * GPA1CON[2] = I2C_3_SDA (3)
 538          * GPA1CON[3] = I2C_3_SCL (3)
 539          */
 540
 541         for (i = 0; i < 4; i++) {
 542                 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
 543                 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
 544         }
 545
 546         /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
 547         s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
 548         s5p_gpio_direction_output(&gpio2->y4, 7, 1);
 549 }
 550
 551 int board_early_init_f(void)
 552 {
 553         wdt_stop();
 554         pmic_reset();
 555         board_clock_init();
 556         board_uart_init();
 557         board_power_init();
 558
 559         return 0;
 560 }
 561
 562 static void lcd_reset(void)
 563 {
 564         struct exynos4_gpio_part2 *gpio2 =
 565                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 566
 567         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 568         udelay(10000);
 569         s5p_gpio_direction_output(&gpio2->y4, 5, 0);
 570         udelay(10000);
 571         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 572 }
 573
 574 static int lcd_power(void)
 575 {
 576         int ret = 0;
 577         struct pmic *p = pmic_get("MAX8997_PMIC");
 578         if (!p)
 579                 return -ENODEV;
 580
 581         if (pmic_probe(p))
 582                 return 0;
 583
 584         /* LDO15 voltage: 2.2v */
 585         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
 586         /* LDO13 voltage: 3.0v */
 587         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
 588
 589         if (ret) {
 590                 puts("MAX8997 LDO setting error!\n");
 591                 return -1;
 592         }
 593
 594         return 0;
 595 }
 596
 597 static struct mipi_dsim_config dsim_config = {
 598         .e_interface            = DSIM_VIDEO,
 599         .e_virtual_ch           = DSIM_VIRTUAL_CH_0,
 600         .e_pixel_format         = DSIM_24BPP_888,
 601         .e_burst_mode           = DSIM_BURST_SYNC_EVENT,
 602         .e_no_data_lane         = DSIM_DATA_LANE_4,
 603         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 604         .hfp                    = 1,
 605
 606         .p                      = 3,
 607         .m                      = 120,
 608         .s                      = 1,
 609
 610         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 611         .pll_stable_time        = 500,
 612
 613         /* escape clk : 10MHz */
 614         .esc_clk                = 20 * 1000000,
 615
 616         /* stop state holding counter after bta change count 0 ~ 0xfff */
 617         .stop_holding_cnt       = 0x7ff,
 618         /* bta timeout 0 ~ 0xff */
 619         .bta_timeout            = 0xff,
 620         /* lp rx timeout 0 ~ 0xffff */
 621         .rx_timeout             = 0xffff,
 622 };
 623
 624 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
 625         .lcd_panel_info = NULL,
 626         .dsim_config = &dsim_config,
 627 };
 628
 629 static struct mipi_dsim_lcd_device mipi_lcd_device = {
 630         .name   = "s6e8ax0",
 631         .id     = -1,
 632         .bus_id = 0,
 633         .platform_data  = (void *)&s6e8ax0_platform_data,
 634 };
 635
 636 static int mipi_power(void)
 637 {
 638         int ret = 0;
 639         struct pmic *p = pmic_get("MAX8997_PMIC");
 640         if (!p)
 641                 return -ENODEV;
 642
 643         if (pmic_probe(p))
 644                 return 0;
 645
 646         /* LDO3 voltage: 1.1v */
 647         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
 648         /* LDO4 voltage: 1.8v */
 649         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
 650
 651         if (ret) {
 652                 puts("MAX8997 LDO setting error!\n");
 653                 return -1;
 654         }
 655
 656         return 0;
 657 }
 658
 659 vidinfo_t panel_info = {
 660         .vl_freq        = 60,
 661         .vl_col         = 720,
 662         .vl_row         = 1280,
 663         .vl_width       = 720,
 664         .vl_height      = 1280,
 665         .vl_clkp        = CONFIG_SYS_HIGH,
 666         .vl_hsp         = CONFIG_SYS_LOW,
 667         .vl_vsp         = CONFIG_SYS_LOW,
 668         .vl_dp          = CONFIG_SYS_LOW,
 669         .vl_bpix        = 5,    /* Bits per pixel, 2^5 = 32 */
 670
 671         /* s6e8ax0 Panel infomation */
 672         .vl_hspw        = 5,
 673         .vl_hbpd        = 10,
 674         .vl_hfpd        = 10,
 675
 676         .vl_vspw        = 2,
 677         .vl_vbpd        = 1,
 678         .vl_vfpd        = 13,
 679         .vl_cmd_allow_len = 0xf,
 680
 681         .win_id         = 3,
 682         .cfg_gpio       = NULL,
 683         .backlight_on   = NULL,
 684         .lcd_power_on   = NULL, /* lcd_power_on in mipi dsi driver */
 685         .reset_lcd      = lcd_reset,
 686         .dual_lcd_enabled = 0,
 687
 688         .init_delay     = 0,
 689         .power_on_delay = 0,
 690         .reset_delay    = 0,
 691         .interface_mode = FIMD_RGB_INTERFACE,
 692         .mipi_enabled   = 1,
 693 };
 694
 695 void init_panel_info(vidinfo_t *vid)
 696 {
 697         vid->logo_on    = 1,
 698         vid->resolution = HD_RESOLUTION,
 699         vid->rgb_mode   = MODE_RGB_P,
 700
 701 #ifdef CONFIG_TIZEN
 702         get_tizen_logo_info(vid);
 703 #endif
 704
 705         if (hwrevision(2))
 706                 mipi_lcd_device.reverse_panel = 1;
 707
 708         strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
 709         s6e8ax0_platform_data.lcd_power = lcd_power;
 710         s6e8ax0_platform_data.mipi_power = mipi_power;
 711         s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
 712         s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
 713         exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
 714         s6e8ax0_init();
 715         exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
 716
 717         setenv("lcdinfo", "lcd=s6e8ax0");
 718 }