board/samsung/trats/trats.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics
   3  * Heungjun Kim <riverful.kim@samsung.com>
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  * Donghwa Lee <dh09.lee@samsung.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <lcd.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/cpu.h>
  30 #include <asm/arch/gpio.h>
  31 #include <asm/arch/mmc.h>
  32 #include <asm/arch/clock.h>
  33 #include <asm/arch/clk.h>
  34 #include <asm/arch/mipi_dsim.h>
  35 #include <asm/arch/watchdog.h>
  36 #include <asm/arch/power.h>
  37 #include <pmic.h>
  38 #include <usb/s3c_udc.h>
  39 #include <max8997_pmic.h>
  40
  41 #include "setup.h"
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 unsigned int board_rev;
  46
  47 #ifdef CONFIG_REVISION_TAG
  48 u32 get_board_rev(void)
  49 {
  50         return board_rev;
  51 }
  52 #endif
  53
  54 static void check_hw_revision(void);
  55
  56 static int hwrevision(int rev)
  57 {
  58         return (board_rev & 0xf) == rev;
  59 }
  60
  61 int board_init(void)
  62 {
  63         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  64
  65         check_hw_revision();
  66         printf("HW Revision:\t0x%x\n", board_rev);
  67
  68 #if defined(CONFIG_PMIC)
  69         pmic_init();
  70 #endif
  71
  72         return 0;
  73 }
  74
  75 int dram_init(void)
  76 {
  77         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
  78                 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  79
  80         return 0;
  81 }
  82
  83 void dram_init_banksize(void)
  84 {
  85         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  86         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  87         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  88         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  89 }
  90
  91 static unsigned int get_hw_revision(void)
  92 {
  93         struct exynos4_gpio_part1 *gpio =
  94                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
  95         int hwrev = 0;
  96         int i;
  97
  98         /* hw_rev[3:0] == GPE1[3:0] */
  99         for (i = 0; i < 4; i++) {
 100                 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
 101                 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
 102         }
 103
 104         udelay(1);
 105
 106         for (i = 0; i < 4; i++)
 107                 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
 108
 109         debug("hwrev 0x%x\n", hwrev);
 110
 111         return hwrev;
 112 }
 113
 114 static void check_hw_revision(void)
 115 {
 116         int hwrev;
 117
 118         hwrev = get_hw_revision();
 119
 120         board_rev |= hwrev;
 121 }
 122
 123 #ifdef CONFIG_DISPLAY_BOARDINFO
 124 int checkboard(void)
 125 {
 126         puts("Board:\tTRATS\n");
 127         return 0;
 128 }
 129 #endif
 130
 131 #ifdef CONFIG_GENERIC_MMC
 132 int board_mmc_init(bd_t *bis)
 133 {
 134         struct exynos4_gpio_part2 *gpio =
 135                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 136         int i, err;
 137
 138         /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
 139         s5p_gpio_direction_output(&gpio->k0, 2, 1);
 140         s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
 141
 142         /*
 143          * eMMC GPIO:
 144          * SDR 8-bit@48MHz at MMC0
 145          * GPK0[0]      SD_0_CLK(2)
 146          * GPK0[1]      SD_0_CMD(2)
 147          * GPK0[2]      SD_0_CDn        -> Not used
 148          * GPK0[3:6]    SD_0_DATA[0:3](2)
 149          * GPK1[3:6]    SD_0_DATA[0:3](3)
 150          *
 151          * DDR 4-bit@26MHz at MMC4
 152          * GPK0[0]      SD_4_CLK(3)
 153          * GPK0[1]      SD_4_CMD(3)
 154          * GPK0[2]      SD_4_CDn        -> Not used
 155          * GPK0[3:6]    SD_4_DATA[0:3](3)
 156          * GPK1[3:6]    SD_4_DATA[4:7](4)
 157          */
 158         for (i = 0; i < 7; i++) {
 159                 if (i == 2)
 160                         continue;
 161                 /* GPK0[0:6] special function 2 */
 162                 s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
 163                 /* GPK0[0:6] pull disable */
 164                 s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
 165                 /* GPK0[0:6] drv 4x */
 166                 s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
 167         }
 168
 169         for (i = 3; i < 7; i++) {
 170                 /* GPK1[3:6] special function 3 */
 171                 s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
 172                 /* GPK1[3:6] pull disable */
 173                 s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
 174                 /* GPK1[3:6] drv 4x */
 175                 s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
 176         }
 177
 178         /*
 179          * MMC device init
 180          * mmc0  : eMMC (8-bit buswidth)
 181          * mmc2  : SD card (4-bit buswidth)
 182          */
 183         err = s5p_mmc_init(0, 8);
 184
 185         /* T-flash detect */
 186         s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
 187         s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
 188
 189         /*
 190          * Check the T-flash  detect pin
 191          * GPX3[4] T-flash detect pin
 192          */
 193         if (!s5p_gpio_get_value(&gpio->x3, 4)) {
 194                 /*
 195                  * SD card GPIO:
 196                  * GPK2[0]      SD_2_CLK(2)
 197                  * GPK2[1]      SD_2_CMD(2)
 198                  * GPK2[2]      SD_2_CDn        -> Not used
 199                  * GPK2[3:6]    SD_2_DATA[0:3](2)
 200                  */
 201                 for (i = 0; i < 7; i++) {
 202                         if (i == 2)
 203                                 continue;
 204                         /* GPK2[0:6] special function 2 */
 205                         s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
 206                         /* GPK2[0:6] pull disable */
 207                         s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
 208                         /* GPK2[0:6] drv 4x */
 209                         s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
 210                 }
 211                 err = s5p_mmc_init(2, 4);
 212         }
 213
 214         return err;
 215 }
 216 #endif
 217
 218 #ifdef CONFIG_USB_GADGET
 219 static int s5pc210_phy_control(int on)
 220 {
 221         int ret = 0;
 222         struct pmic *p = get_pmic();
 223
 224         if (pmic_probe(p))
 225                 return -1;
 226
 227         if (on) {
 228                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 229                                       ENSAFEOUT1, LDO_ON);
 230                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO);
 231                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO);
 232         } else {
 233                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO);
 234                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO);
 235                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 236                                       ENSAFEOUT1, LDO_OFF);
 237         }
 238
 239         if (ret) {
 240                 puts("MAX8997 LDO setting error!\n");
 241                 return -1;
 242         }
 243
 244         return 0;
 245 }
 246
 247 struct s3c_plat_otg_data s5pc210_otg_data = {
 248         .phy_control    = s5pc210_phy_control,
 249         .regs_phy       = EXYNOS4_USBPHY_BASE,
 250         .regs_otg       = EXYNOS4_USBOTG_BASE,
 251         .usb_phy_ctrl   = EXYNOS4_USBPHY_CONTROL,
 252         .usb_flags      = PHY0_SLEEP,
 253 };
 254 #endif
 255
 256 static void pmic_reset(void)
 257 {
 258         struct exynos4_gpio_part2 *gpio =
 259                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 260
 261         s5p_gpio_direction_output(&gpio->x0, 7, 1);
 262         s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
 263 }
 264
 265 static void board_clock_init(void)
 266 {
 267         struct exynos4_clock *clk =
 268                 (struct exynos4_clock *)samsung_get_base_clock();
 269
 270         writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
 271         writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
 272         writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
 273         writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
 274
 275         writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
 276         writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
 277         writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
 278         writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
 279         writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
 280         writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
 281         writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
 282         writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
 283         writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
 284         writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
 285         writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
 286         writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
 287
 288         writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
 289         writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
 290         writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
 291         writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
 292         writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
 293         writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
 294         writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
 295         writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
 296         writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
 297         writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
 298         writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
 299         writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
 300
 301         writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
 302         writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
 303         writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
 304         writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
 305         writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
 306         writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
 307         writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
 308         writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
 309         writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
 310         writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
 311         writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
 312         writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
 313 }
 314
 315 static void board_power_init(void)
 316 {
 317         struct exynos4_power *pwr =
 318                 (struct exynos4_power *)samsung_get_base_power();
 319
 320         /* PS HOLD */
 321         writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
 322
 323         /* Set power down */
 324         writel(0, (unsigned int)&pwr->cam_configuration);
 325         writel(0, (unsigned int)&pwr->tv_configuration);
 326         writel(0, (unsigned int)&pwr->mfc_configuration);
 327         writel(0, (unsigned int)&pwr->g3d_configuration);
 328         writel(0, (unsigned int)&pwr->lcd1_configuration);
 329         writel(0, (unsigned int)&pwr->gps_configuration);
 330         writel(0, (unsigned int)&pwr->gps_alive_configuration);
 331 }
 332
 333 static void board_uart_init(void)
 334 {
 335         struct exynos4_gpio_part1 *gpio1 =
 336                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 337         struct exynos4_gpio_part2 *gpio2 =
 338                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 339         int i;
 340
 341         /*
 342          * UART2 GPIOs
 343          * GPA1CON[0] = UART_2_RXD(2)
 344          * GPA1CON[1] = UART_2_TXD(2)
 345          * GPA1CON[2] = I2C_3_SDA (3)
 346          * GPA1CON[3] = I2C_3_SCL (3)
 347          */
 348
 349         for (i = 0; i < 4; i++) {
 350                 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
 351                 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
 352         }
 353
 354         /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
 355         s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
 356         s5p_gpio_direction_output(&gpio2->y4, 7, 1);
 357 }
 358
 359 int board_early_init_f(void)
 360 {
 361         wdt_stop();
 362         pmic_reset();
 363         board_clock_init();
 364         board_uart_init();
 365         board_power_init();
 366
 367         return 0;
 368 }
 369
 370 static void lcd_reset(void)
 371 {
 372         struct exynos4_gpio_part2 *gpio2 =
 373                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 374
 375         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 376         udelay(10000);
 377         s5p_gpio_direction_output(&gpio2->y4, 5, 0);
 378         udelay(10000);
 379         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 380 }
 381
 382 static int lcd_power(void)
 383 {
 384         int ret = 0;
 385         struct pmic *p = get_pmic();
 386
 387         if (pmic_probe(p))
 388                 return 0;
 389
 390         /* LDO15 voltage: 2.2v */
 391         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
 392         /* LDO13 voltage: 3.0v */
 393         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
 394
 395         if (ret) {
 396                 puts("MAX8997 LDO setting error!\n");
 397                 return -1;
 398         }
 399
 400         return 0;
 401 }
 402
 403 static struct mipi_dsim_config dsim_config = {
 404         .e_interface            = DSIM_VIDEO,
 405         .e_virtual_ch           = DSIM_VIRTUAL_CH_0,
 406         .e_pixel_format         = DSIM_24BPP_888,
 407         .e_burst_mode           = DSIM_BURST_SYNC_EVENT,
 408         .e_no_data_lane         = DSIM_DATA_LANE_4,
 409         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 410         .hfp                    = 1,
 411
 412         .p                      = 3,
 413         .m                      = 120,
 414         .s                      = 1,
 415
 416         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 417         .pll_stable_time        = 500,
 418
 419         /* escape clk : 10MHz */
 420         .esc_clk                = 20 * 1000000,
 421
 422         /* stop state holding counter after bta change count 0 ~ 0xfff */
 423         .stop_holding_cnt       = 0x7ff,
 424         /* bta timeout 0 ~ 0xff */
 425         .bta_timeout            = 0xff,
 426         /* lp rx timeout 0 ~ 0xffff */
 427         .rx_timeout             = 0xffff,
 428 };
 429
 430 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
 431         .lcd_panel_info = NULL,
 432         .dsim_config = &dsim_config,
 433 };
 434
 435 static struct mipi_dsim_lcd_device mipi_lcd_device = {
 436         .name   = "s6e8ax0",
 437         .id     = -1,
 438         .bus_id = 0,
 439         .platform_data  = (void *)&s6e8ax0_platform_data,
 440 };
 441
 442 static int mipi_power(void)
 443 {
 444         int ret = 0;
 445         struct pmic *p = get_pmic();
 446
 447         if (pmic_probe(p))
 448                 return 0;
 449
 450         /* LDO3 voltage: 1.1v */
 451         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
 452         /* LDO4 voltage: 1.8v */
 453         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
 454
 455         if (ret) {
 456                 puts("MAX8997 LDO setting error!\n");
 457                 return -1;
 458         }
 459
 460         return 0;
 461 }
 462
 463 void init_panel_info(vidinfo_t *vid)
 464 {
 465         vid->vl_freq    = 60;
 466         vid->vl_col     = 720;
 467         vid->vl_row     = 1280;
 468         vid->vl_width   = 720;
 469         vid->vl_height  = 1280;
 470         vid->vl_clkp    = CONFIG_SYS_HIGH;
 471         vid->vl_hsp     = CONFIG_SYS_LOW;
 472         vid->vl_vsp     = CONFIG_SYS_LOW;
 473         vid->vl_dp      = CONFIG_SYS_LOW;
 474
 475         vid->vl_bpix    = 5;
 476         vid->dual_lcd_enabled = 0;
 477
 478         /* s6e8ax0 Panel */
 479         vid->vl_hspw    = 5;
 480         vid->vl_hbpd    = 10;
 481         vid->vl_hfpd    = 10;
 482
 483         vid->vl_vspw    = 2;
 484         vid->vl_vbpd    = 1;
 485         vid->vl_vfpd    = 13;
 486         vid->vl_cmd_allow_len = 0xf;
 487
 488         vid->win_id = 3;
 489         vid->cfg_gpio = NULL;
 490         vid->backlight_on = NULL;
 491         vid->lcd_power_on = NULL;       /* lcd_power_on in mipi dsi driver */
 492         vid->reset_lcd = lcd_reset;
 493
 494         vid->init_delay = 0;
 495         vid->power_on_delay = 0;
 496         vid->reset_delay = 0;
 497         vid->interface_mode = FIMD_RGB_INTERFACE;
 498         vid->mipi_enabled = 1;
 499
 500         if (hwrevision(2))
 501                 mipi_lcd_device.reverse_panel = 1;
 502
 503         strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
 504         s6e8ax0_platform_data.lcd_power = lcd_power;
 505         s6e8ax0_platform_data.mipi_power = mipi_power;
 506         s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
 507         s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
 508         exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
 509         s6e8ax0_init();
 510         exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
 511
 512         setenv("lcdinfo", "lcd=s6e8ax0");
 513 }