board/samsung/trats/trats.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics
   3  * Heungjun Kim <riverful.kim@samsung.com>
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  * Donghwa Lee <dh09.lee@samsung.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <lcd.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/cpu.h>
  30 #include <asm/arch/gpio.h>
  31 #include <asm/arch/mmc.h>
  32 #include <asm/arch/clock.h>
  33 #include <asm/arch/clk.h>
  34 #include <asm/arch/mipi_dsim.h>
  35 #include <asm/arch/watchdog.h>
  36 #include <asm/arch/power.h>
  37 #include <pmic.h>
  38 #include <usb/s3c_udc.h>
  39 #include <max8997_pmic.h>
  40 #include <libtizen.h>
  41
  42 #include "setup.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 unsigned int board_rev;
  47
  48 #ifdef CONFIG_REVISION_TAG
  49 u32 get_board_rev(void)
  50 {
  51         return board_rev;
  52 }
  53 #endif
  54
  55 static void check_hw_revision(void);
  56
  57 static int hwrevision(int rev)
  58 {
  59         return (board_rev & 0xf) == rev;
  60 }
  61
  62 struct s3c_plat_otg_data s5pc210_otg_data;
  63
  64 int board_init(void)
  65 {
  66         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  67
  68         check_hw_revision();
  69         printf("HW Revision:\t0x%x\n", board_rev);
  70
  71 #if defined(CONFIG_PMIC)
  72         pmic_init();
  73 #endif
  74
  75         return 0;
  76 }
  77
  78 void i2c_init_board(void)
  79 {
  80         struct exynos4_gpio_part1 *gpio1 =
  81                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
  82         struct exynos4_gpio_part2 *gpio2 =
  83                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
  84
  85         /* I2C_5 -> PMIC */
  86         s5p_gpio_direction_output(&gpio1->b, 7, 1);
  87         s5p_gpio_direction_output(&gpio1->b, 6, 1);
  88         /* I2C_9 -> FG */
  89         s5p_gpio_direction_output(&gpio2->y4, 0, 1);
  90         s5p_gpio_direction_output(&gpio2->y4, 1, 1);
  91 }
  92
  93 int dram_init(void)
  94 {
  95         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
  96                 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
  97                 get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
  98                 get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
  99
 100         return 0;
 101 }
 102
 103 void dram_init_banksize(void)
 104 {
 105         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 106         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 107         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 108         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 109         gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
 110         gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
 111         gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
 112         gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
 113 }
 114
 115 static unsigned int get_hw_revision(void)
 116 {
 117         struct exynos4_gpio_part1 *gpio =
 118                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 119         int hwrev = 0;
 120         int i;
 121
 122         /* hw_rev[3:0] == GPE1[3:0] */
 123         for (i = 0; i < 4; i++) {
 124                 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
 125                 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
 126         }
 127
 128         udelay(1);
 129
 130         for (i = 0; i < 4; i++)
 131                 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
 132
 133         debug("hwrev 0x%x\n", hwrev);
 134
 135         return hwrev;
 136 }
 137
 138 static void check_hw_revision(void)
 139 {
 140         int hwrev;
 141
 142         hwrev = get_hw_revision();
 143
 144         board_rev |= hwrev;
 145 }
 146
 147 #ifdef CONFIG_DISPLAY_BOARDINFO
 148 int checkboard(void)
 149 {
 150         puts("Board:\tTRATS\n");
 151         return 0;
 152 }
 153 #endif
 154
 155 #ifdef CONFIG_GENERIC_MMC
 156 int board_mmc_init(bd_t *bis)
 157 {
 158         struct exynos4_gpio_part2 *gpio =
 159                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 160         int i, err;
 161
 162         /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
 163         s5p_gpio_direction_output(&gpio->k0, 2, 1);
 164         s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
 165
 166         /*
 167          * eMMC GPIO:
 168          * SDR 8-bit@48MHz at MMC0
 169          * GPK0[0]      SD_0_CLK(2)
 170          * GPK0[1]      SD_0_CMD(2)
 171          * GPK0[2]      SD_0_CDn        -> Not used
 172          * GPK0[3:6]    SD_0_DATA[0:3](2)
 173          * GPK1[3:6]    SD_0_DATA[0:3](3)
 174          *
 175          * DDR 4-bit@26MHz at MMC4
 176          * GPK0[0]      SD_4_CLK(3)
 177          * GPK0[1]      SD_4_CMD(3)
 178          * GPK0[2]      SD_4_CDn        -> Not used
 179          * GPK0[3:6]    SD_4_DATA[0:3](3)
 180          * GPK1[3:6]    SD_4_DATA[4:7](4)
 181          */
 182         for (i = 0; i < 7; i++) {
 183                 if (i == 2)
 184                         continue;
 185                 /* GPK0[0:6] special function 2 */
 186                 s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
 187                 /* GPK0[0:6] pull disable */
 188                 s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
 189                 /* GPK0[0:6] drv 4x */
 190                 s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
 191         }
 192
 193         for (i = 3; i < 7; i++) {
 194                 /* GPK1[3:6] special function 3 */
 195                 s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
 196                 /* GPK1[3:6] pull disable */
 197                 s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
 198                 /* GPK1[3:6] drv 4x */
 199                 s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
 200         }
 201
 202         /*
 203          * MMC device init
 204          * mmc0  : eMMC (8-bit buswidth)
 205          * mmc2  : SD card (4-bit buswidth)
 206          */
 207         err = s5p_mmc_init(0, 8);
 208
 209         /* T-flash detect */
 210         s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
 211         s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
 212
 213         /*
 214          * Check the T-flash  detect pin
 215          * GPX3[4] T-flash detect pin
 216          */
 217         if (!s5p_gpio_get_value(&gpio->x3, 4)) {
 218                 /*
 219                  * SD card GPIO:
 220                  * GPK2[0]      SD_2_CLK(2)
 221                  * GPK2[1]      SD_2_CMD(2)
 222                  * GPK2[2]      SD_2_CDn        -> Not used
 223                  * GPK2[3:6]    SD_2_DATA[0:3](2)
 224                  */
 225                 for (i = 0; i < 7; i++) {
 226                         if (i == 2)
 227                                 continue;
 228                         /* GPK2[0:6] special function 2 */
 229                         s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
 230                         /* GPK2[0:6] pull disable */
 231                         s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
 232                         /* GPK2[0:6] drv 4x */
 233                         s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
 234                 }
 235                 err = s5p_mmc_init(2, 4);
 236         }
 237
 238         return err;
 239 }
 240 #endif
 241
 242 #ifdef CONFIG_USB_GADGET
 243 static int s5pc210_phy_control(int on)
 244 {
 245         int ret = 0;
 246         u32 val = 0;
 247         struct pmic *p = get_pmic();
 248
 249         if (pmic_probe(p))
 250                 return -1;
 251
 252         if (on) {
 253                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 254                                       ENSAFEOUT1, LDO_ON);
 255                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 256                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
 257
 258                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 259                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
 260         } else {
 261                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 262                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
 263
 264                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 265                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
 266                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 267                                       ENSAFEOUT1, LDO_OFF);
 268         }
 269
 270         if (ret) {
 271                 puts("MAX8997 LDO setting error!\n");
 272                 return -1;
 273         }
 274
 275         return 0;
 276 }
 277
 278 struct s3c_plat_otg_data s5pc210_otg_data = {
 279         .phy_control    = s5pc210_phy_control,
 280         .regs_phy       = EXYNOS4_USBPHY_BASE,
 281         .regs_otg       = EXYNOS4_USBOTG_BASE,
 282         .usb_phy_ctrl   = EXYNOS4_USBPHY_CONTROL,
 283         .usb_flags      = PHY0_SLEEP,
 284 };
 285
 286 void board_usb_init(void)
 287 {
 288         debug("USB_udc_probe\n");
 289         s3c_udc_probe(&s5pc210_otg_data);
 290 }
 291 #endif
 292
 293 static void pmic_reset(void)
 294 {
 295         struct exynos4_gpio_part2 *gpio =
 296                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 297
 298         s5p_gpio_direction_output(&gpio->x0, 7, 1);
 299         s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
 300 }
 301
 302 static void board_clock_init(void)
 303 {
 304         struct exynos4_clock *clk =
 305                 (struct exynos4_clock *)samsung_get_base_clock();
 306
 307         writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
 308         writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
 309         writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
 310         writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
 311
 312         writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
 313         writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
 314         writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
 315         writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
 316         writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
 317         writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
 318         writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
 319         writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
 320         writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
 321         writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
 322         writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
 323         writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
 324
 325         writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
 326         writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
 327         writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
 328         writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
 329         writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
 330         writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
 331         writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
 332         writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
 333         writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
 334         writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
 335         writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
 336         writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
 337
 338         writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
 339         writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
 340         writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
 341         writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
 342         writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
 343         writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
 344         writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
 345         writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
 346         writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
 347         writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
 348         writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
 349         writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
 350 }
 351
 352 static void board_power_init(void)
 353 {
 354         struct exynos4_power *pwr =
 355                 (struct exynos4_power *)samsung_get_base_power();
 356
 357         /* PS HOLD */
 358         writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
 359
 360         /* Set power down */
 361         writel(0, (unsigned int)&pwr->cam_configuration);
 362         writel(0, (unsigned int)&pwr->tv_configuration);
 363         writel(0, (unsigned int)&pwr->mfc_configuration);
 364         writel(0, (unsigned int)&pwr->g3d_configuration);
 365         writel(0, (unsigned int)&pwr->lcd1_configuration);
 366         writel(0, (unsigned int)&pwr->gps_configuration);
 367         writel(0, (unsigned int)&pwr->gps_alive_configuration);
 368 }
 369
 370 static void board_uart_init(void)
 371 {
 372         struct exynos4_gpio_part1 *gpio1 =
 373                 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
 374         struct exynos4_gpio_part2 *gpio2 =
 375                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 376         int i;
 377
 378         /*
 379          * UART2 GPIOs
 380          * GPA1CON[0] = UART_2_RXD(2)
 381          * GPA1CON[1] = UART_2_TXD(2)
 382          * GPA1CON[2] = I2C_3_SDA (3)
 383          * GPA1CON[3] = I2C_3_SCL (3)
 384          */
 385
 386         for (i = 0; i < 4; i++) {
 387                 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
 388                 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
 389         }
 390
 391         /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
 392         s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
 393         s5p_gpio_direction_output(&gpio2->y4, 7, 1);
 394 }
 395
 396 int board_early_init_f(void)
 397 {
 398         wdt_stop();
 399         pmic_reset();
 400         board_clock_init();
 401         board_uart_init();
 402         board_power_init();
 403
 404         return 0;
 405 }
 406
 407 static void lcd_reset(void)
 408 {
 409         struct exynos4_gpio_part2 *gpio2 =
 410                 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
 411
 412         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 413         udelay(10000);
 414         s5p_gpio_direction_output(&gpio2->y4, 5, 0);
 415         udelay(10000);
 416         s5p_gpio_direction_output(&gpio2->y4, 5, 1);
 417 }
 418
 419 static int lcd_power(void)
 420 {
 421         int ret = 0;
 422         struct pmic *p = get_pmic();
 423
 424         if (pmic_probe(p))
 425                 return 0;
 426
 427         /* LDO15 voltage: 2.2v */
 428         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
 429         /* LDO13 voltage: 3.0v */
 430         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
 431
 432         if (ret) {
 433                 puts("MAX8997 LDO setting error!\n");
 434                 return -1;
 435         }
 436
 437         return 0;
 438 }
 439
 440 static struct mipi_dsim_config dsim_config = {
 441         .e_interface            = DSIM_VIDEO,
 442         .e_virtual_ch           = DSIM_VIRTUAL_CH_0,
 443         .e_pixel_format         = DSIM_24BPP_888,
 444         .e_burst_mode           = DSIM_BURST_SYNC_EVENT,
 445         .e_no_data_lane         = DSIM_DATA_LANE_4,
 446         .e_byte_clk             = DSIM_PLL_OUT_DIV8,
 447         .hfp                    = 1,
 448
 449         .p                      = 3,
 450         .m                      = 120,
 451         .s                      = 1,
 452
 453         /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
 454         .pll_stable_time        = 500,
 455
 456         /* escape clk : 10MHz */
 457         .esc_clk                = 20 * 1000000,
 458
 459         /* stop state holding counter after bta change count 0 ~ 0xfff */
 460         .stop_holding_cnt       = 0x7ff,
 461         /* bta timeout 0 ~ 0xff */
 462         .bta_timeout            = 0xff,
 463         /* lp rx timeout 0 ~ 0xffff */
 464         .rx_timeout             = 0xffff,
 465 };
 466
 467 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
 468         .lcd_panel_info = NULL,
 469         .dsim_config = &dsim_config,
 470 };
 471
 472 static struct mipi_dsim_lcd_device mipi_lcd_device = {
 473         .name   = "s6e8ax0",
 474         .id     = -1,
 475         .bus_id = 0,
 476         .platform_data  = (void *)&s6e8ax0_platform_data,
 477 };
 478
 479 static int mipi_power(void)
 480 {
 481         int ret = 0;
 482         struct pmic *p = get_pmic();
 483
 484         if (pmic_probe(p))
 485                 return 0;
 486
 487         /* LDO3 voltage: 1.1v */
 488         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
 489         /* LDO4 voltage: 1.8v */
 490         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
 491
 492         if (ret) {
 493                 puts("MAX8997 LDO setting error!\n");
 494                 return -1;
 495         }
 496
 497         return 0;
 498 }
 499
 500 vidinfo_t panel_info = {
 501         .vl_freq        = 60,
 502         .vl_col         = 720,
 503         .vl_row         = 1280,
 504         .vl_width       = 720,
 505         .vl_height      = 1280,
 506         .vl_clkp        = CONFIG_SYS_HIGH,
 507         .vl_hsp         = CONFIG_SYS_LOW,
 508         .vl_vsp         = CONFIG_SYS_LOW,
 509         .vl_dp          = CONFIG_SYS_LOW,
 510         .vl_bpix        = 5,    /* Bits per pixel, 2^5 = 32 */
 511
 512         /* s6e8ax0 Panel infomation */
 513         .vl_hspw        = 5,
 514         .vl_hbpd        = 10,
 515         .vl_hfpd        = 10,
 516
 517         .vl_vspw        = 2,
 518         .vl_vbpd        = 1,
 519         .vl_vfpd        = 13,
 520         .vl_cmd_allow_len = 0xf,
 521
 522         .win_id         = 3,
 523         .cfg_gpio       = NULL,
 524         .backlight_on   = NULL,
 525         .lcd_power_on   = NULL, /* lcd_power_on in mipi dsi driver */
 526         .reset_lcd      = lcd_reset,
 527         .dual_lcd_enabled = 0,
 528
 529         .init_delay     = 0,
 530         .power_on_delay = 0,
 531         .reset_delay    = 0,
 532         .interface_mode = FIMD_RGB_INTERFACE,
 533         .mipi_enabled   = 1,
 534 };
 535
 536 void init_panel_info(vidinfo_t *vid)
 537 {
 538         vid->logo_on    = 1,
 539         vid->resolution = HD_RESOLUTION,
 540         vid->rgb_mode   = MODE_RGB_P,
 541
 542 #ifdef CONFIG_TIZEN
 543         get_tizen_logo_info(vid);
 544 #endif
 545
 546         if (hwrevision(2))
 547                 mipi_lcd_device.reverse_panel = 1;
 548
 549         strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
 550         s6e8ax0_platform_data.lcd_power = lcd_power;
 551         s6e8ax0_platform_data.mipi_power = mipi_power;
 552         s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
 553         s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
 554         exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
 555         s6e8ax0_init();
 556         exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
 557
 558         setenv("lcdinfo", "lcd=s6e8ax0");
 559 }