board/samsung/trats/trats.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics
   3  * Heungjun Kim <riverful.kim@samsung.com>
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  * Donghwa Lee <dh09.lee@samsung.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <lcd.h>
  12 #include <asm/io.h>
  13 #include <asm/gpio.h>
  14 #include <asm/arch/cpu.h>
  15 #include <asm/arch/pinmux.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/mipi_dsim.h>
  18 #include <asm/arch/watchdog.h>
  19 #include <asm/arch/power.h>
  20 #include <power/pmic.h>
  21 #include <usb/dwc2_udc.h>
  22 #include <power/max8997_pmic.h>
  23 #include <power/max8997_muic.h>
  24 #include <power/battery.h>
  25 #include <power/max17042_fg.h>
  26 #include <power/pmic.h>
  27 #include <libtizen.h>
  28 #include <usb.h>
  29 #include <usb_mass_storage.h>
  30
  31 #include "setup.h"
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 unsigned int board_rev;
  36
  37 #ifdef CONFIG_REVISION_TAG
  38 u32 get_board_rev(void)
  39 {
  40         return board_rev;
  41 }
  42 #endif
  43
  44 static void check_hw_revision(void);
  45 struct dwc2_plat_otg_data s5pc210_otg_data;
  46
  47 int exynos_init(void)
  48 {
  49         check_hw_revision();
  50         printf("HW Revision:\t0x%x\n", board_rev);
  51
  52         return 0;
  53 }
  54
  55 void i2c_init_board(void)
  56 {
  57 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
  58         int err;
  59
  60         /* I2C_8 -> FG */
  61         gpio_request(EXYNOS4_GPIO_Y40, "i2c_clk");
  62         gpio_request(EXYNOS4_GPIO_Y41, "i2c_data");
  63         gpio_direction_output(EXYNOS4_GPIO_Y40, 1);
  64         gpio_direction_output(EXYNOS4_GPIO_Y41, 1);
  65 #endif
  66 }
  67
  68 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
  69 static void trats_low_power_mode(void)
  70 {
  71         struct exynos4_clock *clk =
  72             (struct exynos4_clock *)samsung_get_base_clock();
  73         struct exynos4_power *pwr =
  74             (struct exynos4_power *)samsung_get_base_power();
  75
  76         /* Power down CORE1 */
  77         /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
  78         writel(0x0, &pwr->arm_core1_configuration);
  79
  80         /* Change the APLL frequency */
  81         /* ENABLE (1 enable) | LOCKED (1 locked)  */
  82         /* [31]              | [29]               */
  83         /* FSEL      | MDIV          | PDIV            | SDIV */
  84         /* [27]      | [25:16]       | [13:8]          | [2:0]      */
  85         writel(0xa0c80604, &clk->apll_con0);
  86
  87         /* Change CPU0 clock divider */
  88         /* CORE2_RATIO  | APLL_RATIO   | PCLK_DBG_RATIO | ATB_RATIO  */
  89         /* [30:28]      | [26:24]      | [22:20]        | [18:16]    */
  90         /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO   | CORE_RATIO */
  91         /* [14:12]      | [10:8]       | [6:4]          | [2:0]      */
  92         writel(0x00000100, &clk->div_cpu0);
  93
  94         /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
  95         while (readl(&clk->div_stat_cpu0) & 0x1111111)
  96                 continue;
  97
  98         /* Change clock divider ratio for DMC */
  99         /* DMCP_RATIO                  | DMCD_RATIO  */
 100         /* [22:20]                     | [18:16]     */
 101         /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO   | ACP_RATIO */
 102         /* [14:12]   | [10:8]     | [6:4]            | [2:0]     */
 103         writel(0x13113117, &clk->div_dmc0);
 104
 105         /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
 106         while (readl(&clk->div_stat_dmc0) & 0x11111111)
 107                 continue;
 108
 109         /* Turn off unnecessary power domains */
 110         writel(0x0, &pwr->xxti_configuration);  /* XXTI */
 111         writel(0x0, &pwr->cam_configuration);   /* CAM */
 112         writel(0x0, &pwr->tv_configuration);    /* TV */
 113         writel(0x0, &pwr->mfc_configuration);   /* MFC */
 114         writel(0x0, &pwr->g3d_configuration);   /* G3D */
 115         writel(0x0, &pwr->gps_configuration);   /* GPS */
 116         writel(0x0, &pwr->gps_alive_configuration);     /* GPS_ALIVE */
 117
 118         /* Turn off unnecessary clocks */
 119         writel(0x0, &clk->gate_ip_cam); /* CAM */
 120         writel(0x0, &clk->gate_ip_tv);          /* TV */
 121         writel(0x0, &clk->gate_ip_mfc); /* MFC */
 122         writel(0x0, &clk->gate_ip_g3d); /* G3D */
 123         writel(0x0, &clk->gate_ip_image);       /* IMAGE */
 124         writel(0x0, &clk->gate_ip_gps); /* GPS */
 125 }
 126 #endif
 127
 128 int exynos_power_init(void)
 129 {
 130 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
 131         int chrg, ret;
 132         struct power_battery *pb;
 133         struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
 134
 135         /*
 136          * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected
 137          * to logical I2C adapter 0
 138          *
 139          * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
 140          * to logical I2C adapter 1
 141          */
 142         ret = power_fg_init(I2C_9);
 143         ret |= power_muic_init(I2C_5);
 144         ret |= power_bat_init(0);
 145         if (ret)
 146                 return ret;
 147
 148         p_fg = pmic_get("MAX17042_FG");
 149         if (!p_fg) {
 150                 puts("MAX17042_FG: Not found\n");
 151                 return -ENODEV;
 152         }
 153
 154         p_chrg = pmic_get("MAX8997_PMIC");
 155         if (!p_chrg) {
 156                 puts("MAX8997_PMIC: Not found\n");
 157                 return -ENODEV;
 158         }
 159
 160         p_muic = pmic_get("MAX8997_MUIC");
 161         if (!p_muic) {
 162                 puts("MAX8997_MUIC: Not found\n");
 163                 return -ENODEV;
 164         }
 165
 166         p_bat = pmic_get("BAT_TRATS");
 167         if (!p_bat) {
 168                 puts("BAT_TRATS: Not found\n");
 169                 return -ENODEV;
 170         }
 171
 172         p_fg->parent =  p_bat;
 173         p_chrg->parent = p_bat;
 174         p_muic->parent = p_bat;
 175
 176         p_bat->low_power_mode = trats_low_power_mode;
 177         p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
 178
 179         pb = p_bat->pbat;
 180         chrg = p_muic->chrg->chrg_type(p_muic);
 181         debug("CHARGER TYPE: %d\n", chrg);
 182
 183         if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
 184                 puts("No battery detected\n");
 185                 return 0;
 186         }
 187
 188         p_fg->fg->fg_battery_check(p_fg, p_bat);
 189
 190         if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
 191                 puts("CHARGE Battery !\n");
 192 #endif
 193
 194         return 0;
 195 }
 196
 197 static unsigned int get_hw_revision(void)
 198 {
 199         int hwrev = 0;
 200         char str[10];
 201         int i;
 202
 203         /* hw_rev[3:0] == GPE1[3:0] */
 204         for (i = 0; i < 4; i++) {
 205                 int pin = i + EXYNOS4_GPIO_E10;
 206
 207                 sprintf(str, "hw_rev%d", i);
 208                 gpio_request(pin, str);
 209                 gpio_cfg_pin(pin, S5P_GPIO_INPUT);
 210                 gpio_set_pull(pin, S5P_GPIO_PULL_NONE);
 211         }
 212
 213         udelay(1);
 214
 215         for (i = 0; i < 4; i++)
 216                 hwrev |= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i);
 217
 218         debug("hwrev 0x%x\n", hwrev);
 219
 220         return hwrev;
 221 }
 222
 223 static void check_hw_revision(void)
 224 {
 225         int hwrev;
 226
 227         hwrev = get_hw_revision();
 228
 229         board_rev |= hwrev;
 230 }
 231
 232
 233 #ifdef CONFIG_USB_GADGET
 234 static int s5pc210_phy_control(int on)
 235 {
 236         struct udevice *dev;
 237         int reg, ret;
 238
 239         ret = pmic_get("max8997-pmic", &dev);
 240         if (ret)
 241                 return ret;
 242
 243         if (on) {
 244                 reg = pmic_reg_read(dev, MAX8997_REG_SAFEOUTCTRL);
 245                 reg |= ENSAFEOUT1;
 246                 ret = pmic_reg_write(dev, MAX8997_REG_SAFEOUTCTRL, reg);
 247                 if (ret) {
 248                         puts("MAX8997 setting error!\n");
 249                         return ret;
 250                 }
 251                 reg = pmic_reg_read(dev, MAX8997_REG_LDO3CTRL);
 252                 reg |= EN_LDO;
 253                 ret = pmic_reg_write(dev, MAX8997_REG_LDO3CTRL, reg);
 254                 if (ret) {
 255                         puts("MAX8997 setting error!\n");
 256                         return ret;
 257                 }
 258                 reg = pmic_reg_read(dev, MAX8997_REG_LDO8CTRL);
 259                 reg |= EN_LDO;
 260                 ret = pmic_reg_write(dev, MAX8997_REG_LDO8CTRL, reg);
 261                 if (ret) {
 262                         puts("MAX8997 setting error!\n");
 263                         return ret;
 264                 }
 265         } else {
 266                 reg = pmic_reg_read(dev, MAX8997_REG_LDO8CTRL);
 267                 reg &= DIS_LDO;
 268                 ret = pmic_reg_write(dev, MAX8997_REG_LDO8CTRL, reg);
 269                 if (ret) {
 270                         puts("MAX8997 setting error!\n");
 271                         return ret;
 272                 }
 273                 reg = pmic_reg_read(dev, MAX8997_REG_LDO3CTRL);
 274                 reg &= DIS_LDO;
 275                 ret = pmic_reg_write(dev, MAX8997_REG_LDO3CTRL, reg);
 276                 if (ret) {
 277                         puts("MAX8997 setting error!\n");
 278                         return ret;
 279                 }
 280                 reg = pmic_reg_read(dev, MAX8997_REG_SAFEOUTCTRL);
 281                 reg &= ~ENSAFEOUT1;
 282                 ret = pmic_reg_write(dev, MAX8997_REG_SAFEOUTCTRL, reg);
 283                 if (ret) {
 284                         puts("MAX8997 setting error!\n");
 285                         return ret;
 286                 }
 287
 288         }
 289
 290         return 0;
 291 }
 292
 293 struct dwc2_plat_otg_data s5pc210_otg_data = {
 294         .phy_control    = s5pc210_phy_control,
 295         .regs_phy       = EXYNOS4_USBPHY_BASE,
 296         .regs_otg       = EXYNOS4_USBOTG_BASE,
 297         .usb_phy_ctrl   = EXYNOS4_USBPHY_CONTROL,
 298         .usb_flags      = PHY0_SLEEP,
 299 };
 300
 301 int board_usb_init(int index, enum usb_init_type init)
 302 {
 303         debug("USB_udc_probe\n");
 304         return dwc2_udc_probe(&s5pc210_otg_data);
 305 }
 306
 307 int g_dnl_board_usb_cable_connected(void)
 308 {
 309 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
 310         struct pmic *muic = pmic_get("MAX8997_MUIC");
 311         if (!muic)
 312                 return 0;
 313
 314         return !!muic->chrg->chrg_type(muic);
 315 #else
 316         return false;
 317 #endif
 318
 319 }
 320 #endif
 321
 322 static void pmic_reset(void)
 323 {
 324         gpio_direction_output(EXYNOS4_GPIO_X07, 1);
 325         gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE);
 326 }
 327
 328 static void board_clock_init(void)
 329 {
 330         struct exynos4_clock *clk =
 331                 (struct exynos4_clock *)samsung_get_base_clock();
 332
 333         writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
 334         writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
 335         writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
 336         writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
 337
 338         writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
 339         writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
 340         writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
 341         writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
 342         writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
 343         writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
 344         writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
 345         writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
 346         writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
 347         writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
 348         writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
 349         writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
 350
 351         writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
 352         writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
 353         writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
 354         writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
 355         writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
 356         writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
 357         writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
 358         writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
 359         writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
 360         writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
 361         writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
 362         writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
 363
 364         writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
 365         writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
 366         writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
 367         writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
 368         writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
 369         writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
 370         writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
 371         writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
 372         writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
 373         writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
 374         writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
 375         writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
 376 }
 377
 378 static void board_power_init(void)
 379 {
 380         struct exynos4_power *pwr =
 381                 (struct exynos4_power *)samsung_get_base_power();
 382
 383         /* PS HOLD */
 384         writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
 385
 386         /* Set power down */
 387         writel(0, (unsigned int)&pwr->cam_configuration);
 388         writel(0, (unsigned int)&pwr->tv_configuration);
 389         writel(0, (unsigned int)&pwr->mfc_configuration);
 390         writel(0, (unsigned int)&pwr->g3d_configuration);
 391         writel(0, (unsigned int)&pwr->lcd1_configuration);
 392         writel(0, (unsigned int)&pwr->gps_configuration);
 393         writel(0, (unsigned int)&pwr->gps_alive_configuration);
 394
 395         /* It is necessary to power down core 1 */
 396         /* to successfully boot CPU1 in kernel */
 397         writel(0, (unsigned int)&pwr->arm_core1_configuration);
 398 }
 399
 400 static void exynos_uart_init(void)
 401 {
 402         /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
 403         gpio_request(EXYNOS4_GPIO_Y47, "uart_sel");
 404         gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP);
 405         gpio_direction_output(EXYNOS4_GPIO_Y47, 1);
 406 }
 407
 408 int exynos_early_init_f(void)
 409 {
 410         wdt_stop();
 411         pmic_reset();
 412         board_clock_init();
 413         exynos_uart_init();
 414         board_power_init();
 415
 416         return 0;
 417 }
 418
 419 void exynos_reset_lcd(void)
 420 {
 421         gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
 422         gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
 423         udelay(10000);
 424         gpio_direction_output(EXYNOS4_GPIO_Y45, 0);
 425         udelay(10000);
 426         gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
 427 }
 428
 429 int lcd_power(void)
 430 {
 431 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
 432         int ret = 0;
 433         struct pmic *p = pmic_get("MAX8997_PMIC");
 434         if (!p)
 435                 return -ENODEV;
 436
 437         if (pmic_probe(p))
 438                 return 0;
 439
 440         /* LDO15 voltage: 2.2v */
 441         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
 442         /* LDO13 voltage: 3.0v */
 443         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
 444
 445         if (ret) {
 446                 puts("MAX8997 LDO setting error!\n");
 447                 return -1;
 448         }
 449 #endif
 450         return 0;
 451 }
 452
 453 int mipi_power(void)
 454 {
 455 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
 456         int ret = 0;
 457         struct pmic *p = pmic_get("MAX8997_PMIC");
 458         if (!p)
 459                 return -ENODEV;
 460
 461         if (pmic_probe(p))
 462                 return 0;
 463
 464         /* LDO3 voltage: 1.1v */
 465         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
 466         /* LDO4 voltage: 1.8v */
 467         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
 468
 469         if (ret) {
 470                 puts("MAX8997 LDO setting error!\n");
 471                 return -1;
 472         }
 473 #endif
 474         return 0;
 475 }
 476
 477 #ifdef CONFIG_LCD
 478 void exynos_lcd_misc_init(vidinfo_t *vid)
 479 {
 480 #ifdef CONFIG_TIZEN
 481         get_tizen_logo_info(vid);
 482 #endif
 483 #ifdef CONFIG_S6E8AX0
 484         s6e8ax0_init();
 485         setenv("lcdinfo", "lcd=s6e8ax0");
 486 #endif
 487 }
 488 #endif