2 * Copyright (C) 2011 Samsung Electronics
3 * Heungjun Kim <riverful.kim@samsung.com>
4 * Kyungmin Park <kyungmin.park@samsung.com>
5 * Donghwa Lee <dh09.lee@samsung.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/gpio.h>
31 #include <asm/arch/mmc.h>
32 #include <asm/arch/pinmux.h>
33 #include <asm/arch/clock.h>
34 #include <asm/arch/clk.h>
35 #include <asm/arch/mipi_dsim.h>
36 #include <asm/arch/watchdog.h>
37 #include <asm/arch/power.h>
39 #include <usb/s3c_udc.h>
40 #include <max8997_pmic.h>
45 DECLARE_GLOBAL_DATA_PTR;
47 unsigned int board_rev;
49 #ifdef CONFIG_REVISION_TAG
50 u32 get_board_rev(void)
56 static void check_hw_revision(void);
58 static int hwrevision(int rev)
60 return (board_rev & 0xf) == rev;
63 struct s3c_plat_otg_data s5pc210_otg_data;
67 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
70 printf("HW Revision:\t0x%x\n", board_rev);
72 #if defined(CONFIG_PMIC)
79 void i2c_init_board(void)
81 struct exynos4_gpio_part1 *gpio1 =
82 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
83 struct exynos4_gpio_part2 *gpio2 =
84 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
87 s5p_gpio_direction_output(&gpio1->b, 7, 1);
88 s5p_gpio_direction_output(&gpio1->b, 6, 1);
90 s5p_gpio_direction_output(&gpio2->y4, 0, 1);
91 s5p_gpio_direction_output(&gpio2->y4, 1, 1);
96 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
97 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
98 get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
99 get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
104 void dram_init_banksize(void)
106 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
107 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
108 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
109 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
110 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
111 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
112 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
113 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
116 static unsigned int get_hw_revision(void)
118 struct exynos4_gpio_part1 *gpio =
119 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
123 /* hw_rev[3:0] == GPE1[3:0] */
124 for (i = 0; i < 4; i++) {
125 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
126 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
131 for (i = 0; i < 4; i++)
132 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
134 debug("hwrev 0x%x\n", hwrev);
139 static void check_hw_revision(void)
143 hwrev = get_hw_revision();
148 #ifdef CONFIG_DISPLAY_BOARDINFO
151 puts("Board:\tTRATS\n");
156 #ifdef CONFIG_GENERIC_MMC
157 int board_mmc_init(bd_t *bis)
159 struct exynos4_gpio_part2 *gpio =
160 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
163 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
164 s5p_gpio_direction_output(&gpio->k0, 2, 1);
165 s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
169 * mmc0 : eMMC (8-bit buswidth)
170 * mmc2 : SD card (4-bit buswidth)
172 err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
174 debug("SDMMC0 not configured\n");
176 err = s5p_mmc_init(0, 8);
179 s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
180 s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
183 * Check the T-flash detect pin
184 * GPX3[4] T-flash detect pin
186 if (!s5p_gpio_get_value(&gpio->x3, 4)) {
187 err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
189 debug("SDMMC2 not configured\n");
191 err = s5p_mmc_init(2, 4);
198 #ifdef CONFIG_USB_GADGET
199 static int s5pc210_phy_control(int on)
203 struct pmic *p = get_pmic();
209 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
211 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
212 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
214 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
215 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
217 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
218 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
220 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
221 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
222 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
223 ENSAFEOUT1, LDO_OFF);
227 puts("MAX8997 LDO setting error!\n");
234 struct s3c_plat_otg_data s5pc210_otg_data = {
235 .phy_control = s5pc210_phy_control,
236 .regs_phy = EXYNOS4_USBPHY_BASE,
237 .regs_otg = EXYNOS4_USBOTG_BASE,
238 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
239 .usb_flags = PHY0_SLEEP,
242 void board_usb_init(void)
244 debug("USB_udc_probe\n");
245 s3c_udc_probe(&s5pc210_otg_data);
249 static void pmic_reset(void)
251 struct exynos4_gpio_part2 *gpio =
252 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
254 s5p_gpio_direction_output(&gpio->x0, 7, 1);
255 s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
258 static void board_clock_init(void)
260 struct exynos4_clock *clk =
261 (struct exynos4_clock *)samsung_get_base_clock();
263 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
264 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
265 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
266 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
268 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
269 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
270 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
271 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
272 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
273 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
274 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
275 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
276 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
277 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
278 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
279 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
281 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
282 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
283 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
284 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
285 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
286 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
287 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
288 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
289 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
290 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
291 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
292 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
294 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
295 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
296 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
297 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
298 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
299 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
300 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
301 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
302 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
303 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
304 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
305 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
308 static void board_power_init(void)
310 struct exynos4_power *pwr =
311 (struct exynos4_power *)samsung_get_base_power();
314 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
317 writel(0, (unsigned int)&pwr->cam_configuration);
318 writel(0, (unsigned int)&pwr->tv_configuration);
319 writel(0, (unsigned int)&pwr->mfc_configuration);
320 writel(0, (unsigned int)&pwr->g3d_configuration);
321 writel(0, (unsigned int)&pwr->lcd1_configuration);
322 writel(0, (unsigned int)&pwr->gps_configuration);
323 writel(0, (unsigned int)&pwr->gps_alive_configuration);
326 static void board_uart_init(void)
328 struct exynos4_gpio_part1 *gpio1 =
329 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
330 struct exynos4_gpio_part2 *gpio2 =
331 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
336 * GPA1CON[0] = UART_2_RXD(2)
337 * GPA1CON[1] = UART_2_TXD(2)
338 * GPA1CON[2] = I2C_3_SDA (3)
339 * GPA1CON[3] = I2C_3_SCL (3)
342 for (i = 0; i < 4; i++) {
343 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
344 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
347 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
348 s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
349 s5p_gpio_direction_output(&gpio2->y4, 7, 1);
352 int board_early_init_f(void)
363 static void lcd_reset(void)
365 struct exynos4_gpio_part2 *gpio2 =
366 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
368 s5p_gpio_direction_output(&gpio2->y4, 5, 1);
370 s5p_gpio_direction_output(&gpio2->y4, 5, 0);
372 s5p_gpio_direction_output(&gpio2->y4, 5, 1);
375 static int lcd_power(void)
378 struct pmic *p = get_pmic();
383 /* LDO15 voltage: 2.2v */
384 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
385 /* LDO13 voltage: 3.0v */
386 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
389 puts("MAX8997 LDO setting error!\n");
396 static struct mipi_dsim_config dsim_config = {
397 .e_interface = DSIM_VIDEO,
398 .e_virtual_ch = DSIM_VIRTUAL_CH_0,
399 .e_pixel_format = DSIM_24BPP_888,
400 .e_burst_mode = DSIM_BURST_SYNC_EVENT,
401 .e_no_data_lane = DSIM_DATA_LANE_4,
402 .e_byte_clk = DSIM_PLL_OUT_DIV8,
409 /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
410 .pll_stable_time = 500,
412 /* escape clk : 10MHz */
413 .esc_clk = 20 * 1000000,
415 /* stop state holding counter after bta change count 0 ~ 0xfff */
416 .stop_holding_cnt = 0x7ff,
417 /* bta timeout 0 ~ 0xff */
419 /* lp rx timeout 0 ~ 0xffff */
420 .rx_timeout = 0xffff,
423 static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
424 .lcd_panel_info = NULL,
425 .dsim_config = &dsim_config,
428 static struct mipi_dsim_lcd_device mipi_lcd_device = {
432 .platform_data = (void *)&s6e8ax0_platform_data,
435 static int mipi_power(void)
438 struct pmic *p = get_pmic();
443 /* LDO3 voltage: 1.1v */
444 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
445 /* LDO4 voltage: 1.8v */
446 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
449 puts("MAX8997 LDO setting error!\n");
456 vidinfo_t panel_info = {
462 .vl_clkp = CONFIG_SYS_HIGH,
463 .vl_hsp = CONFIG_SYS_LOW,
464 .vl_vsp = CONFIG_SYS_LOW,
465 .vl_dp = CONFIG_SYS_LOW,
466 .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */
468 /* s6e8ax0 Panel infomation */
476 .vl_cmd_allow_len = 0xf,
480 .backlight_on = NULL,
481 .lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */
482 .reset_lcd = lcd_reset,
483 .dual_lcd_enabled = 0,
488 .interface_mode = FIMD_RGB_INTERFACE,
492 void init_panel_info(vidinfo_t *vid)
495 vid->resolution = HD_RESOLUTION,
496 vid->rgb_mode = MODE_RGB_P,
499 get_tizen_logo_info(vid);
503 mipi_lcd_device.reverse_panel = 1;
505 strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
506 s6e8ax0_platform_data.lcd_power = lcd_power;
507 s6e8ax0_platform_data.mipi_power = mipi_power;
508 s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
509 s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
510 exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
512 exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
514 setenv("lcdinfo", "lcd=s6e8ax0");