board/samsung/trats/setup.h

   1 /*
   2  * Machine Specific Values for TRATS board based on EXYNOS4210
   3  *
   4  * Copyright (C) 2011 Samsung Electronics
   5  * Heungjun Kim <riverful.kim@samsung.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #ifndef _TRATS_SETUP_H
  27 #define _TRATS_SETUP_H
  28
  29 #include <config.h>
  30 #include <version.h>
  31 #include <asm/arch/cpu.h>
  32
  33 /* CLK_SRC_CPU: APLL(1), MPLL(1), CORE(0), HPM(0) */
  34 #define MUX_HPM_SEL_MOUTAPLL            0x0
  35 #define MUX_HPM_SEL_SCLKMPLL            0x1
  36 #define MUX_CORE_SEL_MOUTAPLL           0x0
  37 #define MUX_CORE_SEL_SCLKMPLL           0x1
  38 #define MUX_MPLL_SEL_FILPLL             0x0
  39 #define MUX_MPLL_SEL_MOUTMPLLFOUT       0x1
  40 #define MUX_APLL_SEL_FILPLL             0x0
  41 #define MUX_APLL_SEL_MOUTMPLLFOUT       0x1
  42 #define CLK_SRC_CPU_VAL                 ((MUX_HPM_SEL_MOUTAPLL << 20) \
  43                                         | (MUX_CORE_SEL_MOUTAPLL << 16) \
  44                                         | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
  45                                         | (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
  46
  47 /* CLK_DIV_CPU0 */
  48 #define APLL_RATIO                      0x0
  49 #define PCLK_DBG_RATIO                  0x1
  50 #define ATB_RATIO                       0x3
  51 #define PERIPH_RATIO                    0x3
  52 #define COREM1_RATIO                    0x7
  53 #define COREM0_RATIO                    0x3
  54 #define CORE_RATIO                      0x0
  55 #define CLK_DIV_CPU0_VAL                ((APLL_RATIO << 24) \
  56                                         | (PCLK_DBG_RATIO << 20) \
  57                                         | (ATB_RATIO << 16) \
  58                                         | (PERIPH_RATIO << 12) \
  59                                         | (COREM1_RATIO << 8) \
  60                                         | (COREM0_RATIO << 4) \
  61                                         | (CORE_RATIO << 0))
  62
  63 /* CLK_DIV_CPU1 */
  64 #define HPM_RATIO                       0x0
  65 #define COPY_RATIO                      0x3
  66 #define CLK_DIV_CPU1_VAL                ((HPM_RATIO << 4) | (COPY_RATIO))
  67
  68 /* CLK_DIV_DMC0 */
  69 #define CORE_TIMERS_RATIO               0x1
  70 #define COPY2_RATIO                     0x3
  71 #define DMCP_RATIO                      0x1
  72 #define DMCD_RATIO                      0x1
  73 #define DMC_RATIO                       0x1
  74 #define DPHY_RATIO                      0x1
  75 #define ACP_PCLK_RATIO                  0x1
  76 #define ACP_RATIO                       0x3
  77 #define CLK_DIV_DMC0_VAL                ((CORE_TIMERS_RATIO << 28) \
  78                                         | (COPY2_RATIO << 24) \
  79                                         | (DMCP_RATIO << 20) \
  80                                         | (DMCD_RATIO << 16) \
  81                                         | (DMC_RATIO << 12) \
  82                                         | (DPHY_RATIO << 8) \
  83                                         | (ACP_PCLK_RATIO << 4) \
  84                                         | (ACP_RATIO << 0))
  85
  86 /* CLK_DIV_DMC1 */
  87 #define DPM_RATIO                       0x1
  88 #define DVSEM_RATIO                     0x1
  89 #define PWI_RATIO                       0x1
  90 #define CLK_DIV_DMC1_VAL                ((DPM_RATIO << 24) \
  91                                         | (DVSEM_RATIO << 16) \
  92                                         | (PWI_RATIO << 8))
  93
  94 /* CLK_SRC_TOP0 */
  95 #define MUX_ONENAND_SEL_ACLK_133        0x0
  96 #define MUX_ONENAND_SEL_ACLK_160        0x1
  97 #define MUX_ACLK_133_SEL_SCLKMPLL       0x0
  98 #define MUX_ACLK_133_SEL_SCLKAPLL       0x1
  99 #define MUX_ACLK_160_SEL_SCLKMPLL       0x0
 100 #define MUX_ACLK_160_SEL_SCLKAPLL       0x1
 101 #define MUX_ACLK_100_SEL_SCLKMPLL       0x0
 102 #define MUX_ACLK_100_SEL_SCLKAPLL       0x1
 103 #define MUX_ACLK_200_SEL_SCLKMPLL       0x0
 104 #define MUX_ACLK_200_SEL_SCLKAPLL       0x1
 105 #define MUX_VPLL_SEL_FINPLL             0x0
 106 #define MUX_VPLL_SEL_FOUTVPLL           0x1
 107 #define MUX_EPLL_SEL_FINPLL             0x0
 108 #define MUX_EPLL_SEL_FOUTEPLL           0x1
 109 #define MUX_ONENAND_1_SEL_MOUTONENAND   0x0
 110 #define MUX_ONENAND_1_SEL_SCLKVPLL      0x1
 111 #define CLK_SRC_TOP0_VAL                ((MUX_ONENAND_SEL_ACLK_160 << 28) \
 112                                         | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
 113                                         | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
 114                                         | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
 115                                         | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
 116                                         | (MUX_VPLL_SEL_FOUTVPLL << 8) \
 117                                         | (MUX_EPLL_SEL_FOUTEPLL << 4) \
 118                                         | (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
 119
 120 /* CLK_DIV_TOP */
 121 #define ONENAND_RATIO                   0x0
 122 #define ACLK_133_RATIO                  0x5
 123 #define ACLK_160_RATIO                  0x4
 124 #define ACLK_100_RATIO                  0x7
 125 #define ACLK_200_RATIO                  0x3
 126 #define CLK_DIV_TOP_VAL                 ((ONENAND_RATIO << 16)  \
 127                                         | (ACLK_133_RATIO << 12)\
 128                                         | (ACLK_160_RATIO << 8) \
 129                                         | (ACLK_100_RATIO << 4) \
 130                                         | (ACLK_200_RATIO << 0))
 131
 132 /* CLK_DIV_LEFTBUS */
 133 #define GPL_RATIO                       0x1
 134 #define GDL_RATIO                       0x3
 135 #define CLK_DIV_LEFTBUS_VAL             ((GPL_RATIO << 4) | (GDL_RATIO))
 136
 137 /* CLK_DIV_RIGHTBUS */
 138 #define GPR_RATIO                       0x1
 139 #define GDR_RATIO                       0x3
 140 #define CLK_DIV_RIGHTBUS_VAL            ((GPR_RATIO << 4) | (GDR_RATIO))
 141
 142 /* CLK_SRS_FSYS: 6 = SCLKMPLL */
 143 #define SATA_SEL_SCLKMPLL               0
 144 #define SATA_SEL_SCLKAPLL               1
 145
 146 #define MMC_SEL_XXTI                    0
 147 #define MMC_SEL_XUSBXTI                 1
 148 #define MMC_SEL_SCLK_HDMI24M            2
 149 #define MMC_SEL_SCLK_USBPHY0            3
 150 #define MMC_SEL_SCLK_USBPHY1            4
 151 #define MMC_SEL_SCLK_HDMIPHY            5
 152 #define MMC_SEL_SCLKMPLL                6
 153 #define MMC_SEL_SCLKEPLL                7
 154 #define MMC_SEL_SCLKVPLL                8
 155
 156 #define MMCC0_SEL                       MMC_SEL_SCLKMPLL
 157 #define MMCC1_SEL                       MMC_SEL_SCLKMPLL
 158 #define MMCC2_SEL                       MMC_SEL_SCLKMPLL
 159 #define MMCC3_SEL                       MMC_SEL_SCLKMPLL
 160 #define MMCC4_SEL                       MMC_SEL_SCLKMPLL
 161 #define CLK_SRC_FSYS_VAL                ((SATA_SEL_SCLKMPLL << 24) \
 162                                         | (MMCC4_SEL << 16) \
 163                                         | (MMCC3_SEL << 12) \
 164                                         | (MMCC2_SEL << 8) \
 165                                         | (MMCC1_SEL << 4) \
 166                                         | (MMCC0_SEL << 0))
 167
 168 /* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
 169 /* CLK_DIV_FSYS1: 800(MPLL) / (15 + 1) */
 170 #define MMC0_RATIO                      0xF
 171 #define MMC0_PRE_RATIO                  0x0
 172 #define MMC1_RATIO                      0xF
 173 #define MMC1_PRE_RATIO                  0x0
 174 #define CLK_DIV_FSYS1_VAL               ((MMC1_PRE_RATIO << 24) \
 175                                         | (MMC1_RATIO << 16) \
 176                                         | (MMC0_PRE_RATIO << 8) \
 177                                         | (MMC0_RATIO << 0))
 178
 179 /* CLK_DIV_FSYS2: 800(MPLL) / (15 + 1) */
 180 #define MMC2_RATIO                      0xF
 181 #define MMC2_PRE_RATIO                  0x0
 182 #define MMC3_RATIO                      0xF
 183 #define MMC3_PRE_RATIO                  0x0
 184 #define CLK_DIV_FSYS2_VAL               ((MMC3_PRE_RATIO << 24) \
 185                                         | (MMC3_RATIO << 16) \
 186                                         | (MMC2_PRE_RATIO << 8) \
 187                                         | (MMC2_RATIO << 0))
 188
 189 /* CLK_DIV_FSYS3: 800(MPLL) / (15 + 1) */
 190 #define MMC4_RATIO                      0xF
 191 #define MMC4_PRE_RATIO                  0x0
 192 #define CLK_DIV_FSYS3_VAL               ((MMC4_PRE_RATIO << 8) \
 193                                         | (MMC4_RATIO << 0))
 194
 195 /* CLK_SRC_PERIL0 */
 196 #define UART_SEL_XXTI                   0
 197 #define UART_SEL_XUSBXTI                1
 198 #define UART_SEL_SCLK_HDMI24M           2
 199 #define UART_SEL_SCLK_USBPHY0           3
 200 #define UART_SEL_SCLK_USBPHY1           4
 201 #define UART_SEL_SCLK_HDMIPHY           5
 202 #define UART_SEL_SCLKMPLL               6
 203 #define UART_SEL_SCLKEPLL               7
 204 #define UART_SEL_SCLKVPLL               8
 205
 206 #define UART0_SEL                       UART_SEL_SCLKMPLL
 207 #define UART1_SEL                       UART_SEL_SCLKMPLL
 208 #define UART2_SEL                       UART_SEL_SCLKMPLL
 209 #define UART3_SEL                       UART_SEL_SCLKMPLL
 210 #define UART4_SEL                       UART_SEL_SCLKMPLL
 211 #define UART5_SEL                       UART_SEL_SCLKMPLL
 212 #define CLK_SRC_PERIL0_VAL              ((UART5_SEL << 16) \
 213                                         | (UART4_SEL << 12) \
 214                                         | (UART3_SEL << 12) \
 215                                         | (UART2_SEL << 8) \
 216                                         | (UART1_SEL << 4) \
 217                                         | (UART0_SEL << 0))
 218
 219 /* SCLK_UART[0-4] = MOUTUART[0-4] / (UART[0-4]_RATIO + 1) */
 220 /* CLK_DIV_PERIL0 */
 221 #define UART0_RATIO                     7
 222 #define UART1_RATIO                     7
 223 #define UART2_RATIO                     7
 224 #define UART3_RATIO                     4
 225 #define UART4_RATIO                     7
 226 #define UART5_RATIO                     7
 227 #define CLK_DIV_PERIL0_VAL              ((UART5_RATIO << 16) \
 228                                         | (UART4_RATIO << 12) \
 229                                         | (UART3_RATIO << 12) \
 230                                         | (UART2_RATIO << 8) \
 231                                         | (UART1_RATIO << 4) \
 232                                         | (UART0_RATIO << 0))
 233
 234 /* CLK_DIV_PERIL3 */
 235 #define SLIMBUS_RATIO                   0x0
 236 #define PWM_RATIO                       0x8
 237 #define CLK_DIV_PERIL3_VAL              ((SLIMBUS_RATIO << 4) \
 238                                         | (PWM_RATIO << 0))
 239
 240 /* Required period to generate a stable clock output */
 241 /* PLL_LOCK_TIME */
 242 #define PLL_LOCKTIME                    0x1C20
 243
 244 /* PLL Values */
 245 #define DISABLE                         0
 246 #define ENABLE                          1
 247 #define SET_PLL(mdiv, pdiv, sdiv)       ((ENABLE << 31)\
 248                                         | (mdiv << 16) \
 249                                         | (pdiv << 8) \
 250                                         | (sdiv << 0))
 251
 252 /* APLL_CON0: 800MHz */
 253 #define APLL_MDIV                       0xC8
 254 #define APLL_PDIV                       0x6
 255 #define APLL_SDIV                       0x1
 256 #define APLL_CON0_VAL                   SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
 257
 258 /* APLL_CON1 */
 259 #define APLL_AFC_ENB                    0x1
 260 #define APLL_AFC                        0x1C
 261 #define APLL_CON1_VAL                   ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
 262
 263 /* MPLL_CON0: 800MHz */
 264 #define MPLL_MDIV                       0xC8
 265 #define MPLL_PDIV                       0x6
 266 #define MPLL_SDIV                       0x1
 267 #define MPLL_CON0_VAL                   SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
 268
 269 /* MPLL_CON1 */
 270 #define MPLL_AFC_ENB                    0x1
 271 #define MPLL_AFC                        0x1C
 272 #define MPLL_CON1_VAL                   ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
 273
 274 /* EPLL_CON0: 96MHz */
 275 #define EPLL_MDIV                       0x30
 276 #define EPLL_PDIV                       0x3
 277 #define EPLL_SDIV                       0x2
 278 #define EPLL_CON0_VAL                   SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
 279
 280 /* EPLL_CON1 */
 281 #define EPLL_K                          0x0
 282 #define EPLL_CON1_VAL                   (EPLL_K >> 0)
 283
 284 /* VPLL_CON0: 108MHz */
 285 #define VPLL_MDIV                       0x35
 286 #define VPLL_PDIV                       0x3
 287 #define VPLL_SDIV                       0x2
 288 #define VPLL_CON0_VAL                   SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
 289
 290 /* VPLL_CON1 */
 291 #define VPLL_SSCG_EN                    DISABLE
 292 #define VPLL_SEL_PF_DN_SPREAD           0x0
 293 #define VPLL_MRR                        0x11
 294 #define VPLL_MFR                        0x0
 295 #define VPLL_K                          0x400
 296 #define VPLL_CON1_VAL                   ((VPLL_SSCG_EN << 31)\
 297                                         | (VPLL_SEL_PF_DN_SPREAD << 29) \
 298                                         | (VPLL_MRR << 24) \
 299                                         | (VPLL_MFR << 16) \
 300                                         | (VPLL_K << 0))
 301
 302 /* CLOCK GATE */
 303 #define CLK_DIS                         0x0
 304 #define CLK_EN                          0x1
 305
 306 #define BIT_CAM_CLK_PIXELASYNCM1        18
 307 #define BIT_CAM_CLK_PIXELASYNCM0        17
 308 #define BIT_CAM_CLK_PPMUCAMIF           16
 309 #define BIT_CAM_CLK_QEFIMC3             15
 310 #define BIT_CAM_CLK_QEFIMC2             14
 311 #define BIT_CAM_CLK_QEFIMC1             13
 312 #define BIT_CAM_CLK_QEFIMC0             12
 313 #define BIT_CAM_CLK_SMMUJPEG            11
 314 #define BIT_CAM_CLK_SMMUFIMC3           10
 315 #define BIT_CAM_CLK_SMMUFIMC2           9
 316 #define BIT_CAM_CLK_SMMUFIMC1           8
 317 #define BIT_CAM_CLK_SMMUFIMC0           7
 318 #define BIT_CAM_CLK_JPEG                6
 319 #define BIT_CAM_CLK_CSIS1               5
 320 #define BIT_CAM_CLK_CSIS0               4
 321 #define BIT_CAM_CLK_FIMC3               3
 322 #define BIT_CAM_CLK_FIMC2               2
 323 #define BIT_CAM_CLK_FIMC1               1
 324 #define BIT_CAM_CLK_FIMC0               0
 325 #define CLK_GATE_IP_CAM_ALL_EN          ((CLK_EN << BIT_CAM_CLK_PIXELASYNCM1)\
 326                                         | (CLK_EN << BIT_CAM_CLK_PIXELASYNCM0)\
 327                                         | (CLK_EN << BIT_CAM_CLK_PPMUCAMIF)\
 328                                         | (CLK_EN << BIT_CAM_CLK_QEFIMC3)\
 329                                         | (CLK_EN << BIT_CAM_CLK_QEFIMC2)\
 330                                         | (CLK_EN << BIT_CAM_CLK_QEFIMC1)\
 331                                         | (CLK_EN << BIT_CAM_CLK_QEFIMC0)\
 332                                         | (CLK_EN << BIT_CAM_CLK_SMMUJPEG)\
 333                                         | (CLK_EN << BIT_CAM_CLK_SMMUFIMC3)\
 334                                         | (CLK_EN << BIT_CAM_CLK_SMMUFIMC2)\
 335                                         | (CLK_EN << BIT_CAM_CLK_SMMUFIMC1)\
 336                                         | (CLK_EN << BIT_CAM_CLK_SMMUFIMC0)\
 337                                         | (CLK_EN << BIT_CAM_CLK_JPEG)\
 338                                         | (CLK_EN << BIT_CAM_CLK_CSIS1)\
 339                                         | (CLK_EN << BIT_CAM_CLK_CSIS0)\
 340                                         | (CLK_EN << BIT_CAM_CLK_FIMC3)\
 341                                         | (CLK_EN << BIT_CAM_CLK_FIMC2)\
 342                                         | (CLK_EN << BIT_CAM_CLK_FIMC1)\
 343                                         | (CLK_EN << BIT_CAM_CLK_FIMC0))
 344 #define CLK_GATE_IP_CAM_ALL_DIS         ~CLK_GATE_IP_CAM_ALL_EN
 345
 346 #define BIT_VP_CLK_PPMUTV               5
 347 #define BIT_VP_CLK_SMMUTV               4
 348 #define BIT_VP_CLK_HDMI                 3
 349 #define BIT_VP_CLK_TVENC                2
 350 #define BIT_VP_CLK_MIXER                1
 351 #define BIT_VP_CLK_VP                   0
 352 #define CLK_GATE_IP_VP_ALL_EN           ((CLK_EN << BIT_VP_CLK_PPMUTV)\
 353                                         | (CLK_EN << BIT_VP_CLK_SMMUTV)\
 354                                         | (CLK_EN << BIT_VP_CLK_HDMI)\
 355                                         | (CLK_EN << BIT_VP_CLK_TVENC)\
 356                                         | (CLK_EN << BIT_VP_CLK_MIXER)\
 357                                         | (CLK_EN << BIT_VP_CLK_VP))
 358 #define CLK_GATE_IP_VP_ALL_DIS          ~CLK_GATE_IP_VP_ALL_EN
 359
 360 #define BIT_MFC_CLK_PPMUMFC_R           4
 361 #define BIT_MFC_CLK_PPMUMFC_L           3
 362 #define BIT_MFC_CLK_SMMUMFC_R           2
 363 #define BIT_MFC_CLK_SMMUMFC_L           1
 364 #define BIT_MFC_CLK_MFC                 0
 365 #define CLK_GATE_IP_MFC_ALL_EN          ((CLK_EN << BIT_MFC_CLK_PPMUMFC_R)\
 366                                         | (CLK_EN << BIT_MFC_CLK_PPMUMFC_L)\
 367                                         | (CLK_EN << BIT_MFC_CLK_SMMUMFC_R)\
 368                                         | (CLK_EN << BIT_MFC_CLK_SMMUMFC_L)\
 369                                         | (CLK_EN << BIT_MFC_CLK_MFC))
 370 #define CLK_GATE_IP_MFC_ALL_DIS         ~CLK_GATE_IP_MFC_ALL_EN
 371
 372 #define BIT_G3D_CLK_QEG3D               2
 373 #define BIT_G3D_CLK_PPMUG3D             1
 374 #define BIT_G3D_CLK_G3D                 0
 375 #define CLK_GATE_IP_G3D_ALL_EN          ((CLK_EN << BIT_G3D_CLK_QEG3D)\
 376                                         | (CLK_EN << BIT_G3D_CLK_PPMUG3D)\
 377                                         | (CLK_EN << BIT_G3D_CLK_G3D))
 378 #define CLK_GATE_IP_G3D_ALL_DIS         ~CLK_GATE_IP_G3D_ALL_EN
 379
 380 #define BIT_IMAGE_CLK_PPMUIMAGE         9
 381 #define BIT_IMAGE_CLK_QEMDMA            8
 382 #define BIT_IMAGE_CLK_QEROTATOR         7
 383 #define BIT_IMAGE_CLK_QEG2D             6
 384 #define BIT_IMAGE_CLK_SMMUMDMA          5
 385 #define BIT_IMAGE_CLK_SMMUROTATOR       4
 386 #define BIT_IMAGE_CLK_SMMUG2D           3
 387 #define BIT_IMAGE_CLK_MDMA              2
 388 #define BIT_IMAGE_CLK_ROTATOR           1
 389 #define BIT_IMAGE_CLK_G2D               0
 390 #define CLK_GATE_IP_IMAGE_ALL_EN        ((CLK_EN << BIT_IMAGE_CLK_PPMUIMAGE)\
 391                                         | (CLK_EN << BIT_IMAGE_CLK_QEMDMA)\
 392                                         | (CLK_EN << BIT_IMAGE_CLK_QEROTATOR)\
 393                                         | (CLK_EN << BIT_IMAGE_CLK_QEG2D)\
 394                                         | (CLK_EN << BIT_IMAGE_CLK_SMMUMDMA)\
 395                                         | (CLK_EN << BIT_IMAGE_CLK_SMMUROTATOR)\
 396                                         | (CLK_EN << BIT_IMAGE_CLK_SMMUG2D)\
 397                                         | (CLK_EN << BIT_IMAGE_CLK_MDMA)\
 398                                         | (CLK_EN << BIT_IMAGE_CLK_ROTATOR)\
 399                                         | (CLK_EN << BIT_IMAGE_CLK_G2D))
 400 #define CLK_GATE_IP_IMAGE_ALL_DIS       ~CLK_GATE_IP_IMAGE_ALL_EN
 401
 402 #define BIT_LCD0_CLK_PPMULCD0           5
 403 #define BIT_LCD0_CLK_SMMUFIMD0          4
 404 #define BIT_LCD0_CLK_DSIM0              3
 405 #define BIT_LCD0_CLK_MDNIE0             2
 406 #define BIT_LCD0_CLK_MIE0               1
 407 #define BIT_LCD0_CLK_FIMD0              0
 408 #define CLK_GATE_IP_LCD0_ALL_EN         ((CLK_EN << BIT_LCD0_CLK_PPMULCD0)\
 409                                         | (CLK_EN << BIT_LCD0_CLK_SMMUFIMD0)\
 410                                         | (CLK_EN << BIT_LCD0_CLK_DSIM0)\
 411                                         | (CLK_EN << BIT_LCD0_CLK_MDNIE0)\
 412                                         | (CLK_EN << BIT_LCD0_CLK_MIE0)\
 413                                         | (CLK_EN << BIT_LCD0_CLK_FIMD0))
 414 #define CLK_GATE_IP_LCD0_ALL_DIS        ~CLK_GATE_IP_LCD0_ALL_EN
 415
 416 #define BIT_LCD1_CLK_PPMULCD1           5
 417 #define BIT_LCD1_CLK_SMMUFIMD1          4
 418 #define BIT_LCD1_CLK_DSIM1              3
 419 #define BIT_LCD1_CLK_MDNIE1             2
 420 #define BIT_LCD1_CLK_MIE1               1
 421 #define BIT_LCD1_CLK_FIMD1              0
 422 #define CLK_GATE_IP_LCD1_ALL_EN         ((CLK_EN << BIT_LCD1_CLK_PPMULCD1)\
 423                                         | (CLK_EN << BIT_LCD1_CLK_SMMUFIMD1)\
 424                                         | (CLK_EN << BIT_LCD1_CLK_DSIM1)\
 425                                         | (CLK_EN << BIT_LCD1_CLK_MDNIE1)\
 426                                         | (CLK_EN << BIT_LCD1_CLK_MIE1)\
 427                                         | (CLK_EN << BIT_LCD1_CLK_FIMD1))
 428 #define CLK_GATE_IP_LCD1_ALL_DIS        ~CLK_GATE_IP_LCD1_ALL_EN
 429
 430 #define BIT_FSYS_CLK_SMMUPCIE           18
 431 #define BIT_FSYS_CLK_PPMUFILE           17
 432 #define BIT_FSYS_CLK_NFCON              16
 433 #define BIT_FSYS_CLK_ONENAND            15
 434 #define BIT_FSYS_CLK_PCIE               14
 435 #define BIT_FSYS_CLK_USBDEVICE          13
 436 #define BIT_FSYS_CLK_USBHOST            12
 437 #define BIT_FSYS_CLK_SROMC              11
 438 #define BIT_FSYS_CLK_SATA               10
 439 #define BIT_FSYS_CLK_SDMMC4             9
 440 #define BIT_FSYS_CLK_SDMMC3             8
 441 #define BIT_FSYS_CLK_SDMMC2             7
 442 #define BIT_FSYS_CLK_SDMMC1             6
 443 #define BIT_FSYS_CLK_SDMMC0             5
 444 #define BIT_FSYS_CLK_TSI                4
 445 #define BIT_FSYS_CLK_SATAPHY            3
 446 #define BIT_FSYS_CLK_PCIEPHY            2
 447 #define BIT_FSYS_CLK_PDMA1              1
 448 #define BIT_FSYS_CLK_PDMA0              0
 449 #define CLK_GATE_IP_FSYS_ALL_EN         ((CLK_EN << BIT_FSYS_CLK_SMMUPCIE)\
 450                                         | (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
 451                                         | (CLK_EN << BIT_FSYS_CLK_NFCON)\
 452                                         | (CLK_EN << BIT_FSYS_CLK_ONENAND)\
 453                                         | (CLK_EN << BIT_FSYS_CLK_PCIE)\
 454                                         | (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
 455                                         | (CLK_EN << BIT_FSYS_CLK_USBHOST)\
 456                                         | (CLK_EN << BIT_FSYS_CLK_SROMC)\
 457                                         | (CLK_EN << BIT_FSYS_CLK_SATA)\
 458                                         | (CLK_EN << BIT_FSYS_CLK_SDMMC4)\
 459                                         | (CLK_EN << BIT_FSYS_CLK_SDMMC3)\
 460                                         | (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
 461                                         | (CLK_EN << BIT_FSYS_CLK_SDMMC1)\
 462                                         | (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
 463                                         | (CLK_EN << BIT_FSYS_CLK_TSI)\
 464                                         | (CLK_EN << BIT_FSYS_CLK_SATAPHY)\
 465                                         | (CLK_EN << BIT_FSYS_CLK_PCIEPHY)\
 466                                         | (CLK_EN << BIT_FSYS_CLK_PDMA1)\
 467                                         | (CLK_EN << BIT_FSYS_CLK_PDMA0))
 468 #define CLK_GATE_IP_FSYS_ALL_DIS        ~CLK_GATE_IP_FSYS_ALL_EN
 469
 470 #define BIT_GPS_CLK_SMMUGPS             1
 471 #define BIT_GPS_CLK_GPS                 0
 472 #define CLK_GATE_IP_GPS_ALL_EN          ((CLK_EN << BIT_GPS_CLK_SMMUGPS)\
 473                                         | (CLK_EN << BIT_GPS_CLK_GPS))
 474 #define CLK_GATE_IP_GPS_ALL_DIS         ~CLK_GATE_IP_GPS_ALL_EN
 475
 476 #define BIT_PERIL_CLK_MODEMIF           28
 477 #define BIT_PERIL_CLK_AC97              27
 478 #define BIT_PERIL_CLK_SPDIF             26
 479 #define BIT_PERIL_CLK_SLIMBUS           25
 480 #define BIT_PERIL_CLK_PWM               24
 481 #define BIT_PERIL_CLK_PCM2              23
 482 #define BIT_PERIL_CLK_PCM1              22
 483 #define BIT_PERIL_CLK_I2S2              21
 484 #define BIT_PERIL_CLK_I2S1              20
 485 #define BIT_PERIL_CLK_RESERVED0         19
 486 #define BIT_PERIL_CLK_SPI2              18
 487 #define BIT_PERIL_CLK_SPI1              17
 488 #define BIT_PERIL_CLK_SPI0              16
 489 #define BIT_PERIL_CLK_TSADC             15
 490 #define BIT_PERIL_CLK_I2CHDMI           14
 491 #define BIT_PERIL_CLK_I2C7              13
 492 #define BIT_PERIL_CLK_I2C6              12
 493 #define BIT_PERIL_CLK_I2C5              11
 494 #define BIT_PERIL_CLK_I2C4              10
 495 #define BIT_PERIL_CLK_I2C3              9
 496 #define BIT_PERIL_CLK_I2C2              8
 497 #define BIT_PERIL_CLK_I2C1              7
 498 #define BIT_PERIL_CLK_I2C0              6
 499 #define BIT_PERIL_CLK_RESERVED1         5
 500 #define BIT_PERIL_CLK_UART4             4
 501 #define BIT_PERIL_CLK_UART3             3
 502 #define BIT_PERIL_CLK_UART2             2
 503 #define BIT_PERIL_CLK_UART1             1
 504 #define BIT_PERIL_CLK_UART0             0
 505 #define CLK_GATE_IP_PERIL_ALL_EN        ((CLK_EN << BIT_PERIL_CLK_MODEMIF)\
 506                                         | (CLK_EN << BIT_PERIL_CLK_AC97)\
 507                                         | (CLK_EN << BIT_PERIL_CLK_SPDIF)\
 508                                         | (CLK_EN << BIT_PERIL_CLK_SLIMBUS)\
 509                                         | (CLK_EN << BIT_PERIL_CLK_PWM)\
 510                                         | (CLK_EN << BIT_PERIL_CLK_PCM2)\
 511                                         | (CLK_EN << BIT_PERIL_CLK_PCM1)\
 512                                         | (CLK_EN << BIT_PERIL_CLK_I2S2)\
 513                                         | (CLK_EN << BIT_PERIL_CLK_I2S1)\
 514                                         | (CLK_EN << BIT_PERIL_CLK_RESERVED0)\
 515                                         | (CLK_EN << BIT_PERIL_CLK_SPI2)\
 516                                         | (CLK_EN << BIT_PERIL_CLK_SPI1)\
 517                                         | (CLK_EN << BIT_PERIL_CLK_SPI0)\
 518                                         | (CLK_EN << BIT_PERIL_CLK_TSADC)\
 519                                         | (CLK_EN << BIT_PERIL_CLK_I2CHDMI)\
 520                                         | (CLK_EN << BIT_PERIL_CLK_I2C7)\
 521                                         | (CLK_EN << BIT_PERIL_CLK_I2C6)\
 522                                         | (CLK_EN << BIT_PERIL_CLK_I2C5)\
 523                                         | (CLK_EN << BIT_PERIL_CLK_I2C4)\
 524                                         | (CLK_EN << BIT_PERIL_CLK_I2C3)\
 525                                         | (CLK_EN << BIT_PERIL_CLK_I2C2)\
 526                                         | (CLK_EN << BIT_PERIL_CLK_I2C1)\
 527                                         | (CLK_EN << BIT_PERIL_CLK_I2C0)\
 528                                         | (CLK_EN << BIT_PERIL_CLK_RESERVED1)\
 529                                         | (CLK_EN << BIT_PERIL_CLK_UART4)\
 530                                         | (CLK_EN << BIT_PERIL_CLK_UART3)\
 531                                         | (CLK_EN << BIT_PERIL_CLK_UART2)\
 532                                         | (CLK_EN << BIT_PERIL_CLK_UART1)\
 533                                         | (CLK_EN << BIT_PERIL_CLK_UART0))
 534 #define CLK_GATE_IP_PERIL_ALL_DIS       ~CLK_GATE_IP_PERIL_ALL_EN
 535
 536 #define BIT_PERIR_CLK_TMU_APBIF         17
 537 #define BIT_PERIR_CLK_KEYIF             16
 538 #define BIT_PERIR_CLK_RTC               15
 539 #define BIT_PERIR_CLK_WDT               14
 540 #define BIT_PERIR_CLK_MCT               13
 541 #define BIT_PERIR_CLK_SECKEY            12
 542 #define BIT_PERIR_CLK_HDMI_CEC          11
 543 #define BIT_PERIR_CLK_TZPC5             10
 544 #define BIT_PERIR_CLK_TZPC4             9
 545 #define BIT_PERIR_CLK_TZPC3             8
 546 #define BIT_PERIR_CLK_TZPC2             7
 547 #define BIT_PERIR_CLK_TZPC1             6
 548 #define BIT_PERIR_CLK_TZPC0             5
 549 #define BIT_PERIR_CLK_CMU_DMCPART       4
 550 #define BIT_PERIR_CLK_RESERVED          3
 551 #define BIT_PERIR_CLK_CMU_APBIF         2
 552 #define BIT_PERIR_CLK_SYSREG            1
 553 #define BIT_PERIR_CLK_CHIP_ID           0
 554 #define CLK_GATE_IP_PERIR_ALL_EN        ((CLK_EN << BIT_PERIR_CLK_TMU_APBIF)\
 555                                         | (CLK_EN << BIT_PERIR_CLK_KEYIF)\
 556                                         | (CLK_EN << BIT_PERIR_CLK_RTC)\
 557                                         | (CLK_EN << BIT_PERIR_CLK_WDT)\
 558                                         | (CLK_EN << BIT_PERIR_CLK_MCT)\
 559                                         | (CLK_EN << BIT_PERIR_CLK_SECKEY)\
 560                                         | (CLK_EN << BIT_PERIR_CLK_HDMI_CEC)\
 561                                         | (CLK_EN << BIT_PERIR_CLK_TZPC5)\
 562                                         | (CLK_EN << BIT_PERIR_CLK_TZPC4)\
 563                                         | (CLK_EN << BIT_PERIR_CLK_TZPC3)\
 564                                         | (CLK_EN << BIT_PERIR_CLK_TZPC2)\
 565                                         | (CLK_EN << BIT_PERIR_CLK_TZPC1)\
 566                                         | (CLK_EN << BIT_PERIR_CLK_TZPC0)\
 567                                         | (CLK_EN << BIT_PERIR_CLK_CMU_DMCPART)\
 568                                         | (CLK_EN << BIT_PERIR_CLK_RESERVED)\
 569                                         | (CLK_EN << BIT_PERIR_CLK_CMU_APBIF)\
 570                                         | (CLK_EN << BIT_PERIR_CLK_SYSREG)\
 571                                         | (CLK_EN << BIT_PERIR_CLK_CHIP_ID))
 572 #define CLK_GATE_IP_PERIR_ALL_DIS       ~CLK_GATE_IP_PERIR_ALL_EN
 573
 574 #define BIT_BLOCK_CLK_GPS               7
 575 #define BIT_BLOCK_CLK_RESERVED          6
 576 #define BIT_BLOCK_CLK_LCD1              5
 577 #define BIT_BLOCK_CLK_LCD0              4
 578 #define BIT_BLOCK_CLK_G3D               3
 579 #define BIT_BLOCK_CLK_MFC               2
 580 #define BIT_BLOCK_CLK_TV                1
 581 #define BIT_BLOCK_CLK_CAM               0
 582 #define CLK_GATE_BLOCK_ALL_EN           ((CLK_EN << BIT_BLOCK_CLK_GPS)\
 583                                         | (CLK_EN << BIT_BLOCK_CLK_RESERVED)\
 584                                         | (CLK_EN << BIT_BLOCK_CLK_LCD1)\
 585                                         | (CLK_EN << BIT_BLOCK_CLK_LCD0)\
 586                                         | (CLK_EN << BIT_BLOCK_CLK_G3D)\
 587                                         | (CLK_EN << BIT_BLOCK_CLK_MFC)\
 588                                         | (CLK_EN << BIT_BLOCK_CLK_TV)\
 589                                         | (CLK_EN << BIT_BLOCK_CLK_CAM))
 590 #define CLK_GATE_BLOCK_ALL_DIS          ~CLK_GATE_BLOCK_ALL_EN
 591
 592 /*
 593  * GATE CAM     : All block
 594  * GATE VP      : All block
 595  * GATE MFC     : All block
 596  * GATE G3D     : All block
 597  * GATE IMAGE   : All block
 598  * GATE LCD0    : All block
 599  * GATE LCD1    : All block
 600  * GATE FSYS    : Enable - PDMA0,1, SDMMC0,2, USBHOST, USBDEVICE, PPMUFILE
 601  * GATE GPS     : All block
 602  * GATE PERI Left       : All Enable, Block - SLIMBUS, SPDIF, AC97
 603  * GATE PERI Right      : All Enable, Block - KEYIF
 604  * GATE Block   : All block
 605  */
 606 #define CLK_GATE_IP_CAM_VAL             CLK_GATE_IP_CAM_ALL_DIS
 607 #define CLK_GATE_IP_VP_VAL              CLK_GATE_IP_VP_ALL_DIS
 608 #define CLK_GATE_IP_MFC_VAL             CLK_GATE_IP_MFC_ALL_DIS
 609 #define CLK_GATE_IP_G3D_VAL             CLK_GATE_IP_G3D_ALL_DIS
 610 #define CLK_GATE_IP_IMAGE_VAL           CLK_GATE_IP_IMAGE_ALL_DIS
 611 #define CLK_GATE_IP_LCD0_VAL            CLK_GATE_IP_LCD0_ALL_DIS
 612 #define CLK_GATE_IP_LCD1_VAL            CLK_GATE_IP_LCD1_ALL_DIS
 613 #define CLK_GATE_IP_FSYS_VAL            (CLK_GATE_IP_FSYS_ALL_DIS \
 614                                         | (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
 615                                         | (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
 616                                         | (CLK_EN << BIT_FSYS_CLK_USBHOST)\
 617                                         | (CLK_EN << BIT_FSYS_CLK_SROMC)\
 618                                         | (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
 619                                         | (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
 620                                         | (CLK_EN << BIT_FSYS_CLK_PDMA1)\
 621                                         | (CLK_EN << BIT_FSYS_CLK_PDMA0))
 622 #define CLK_GATE_IP_GPS_VAL             CLK_GATE_IP_GPS_ALL_DIS
 623 #define CLK_GATE_IP_PERIL_VAL           (CLK_GATE_IP_PERIL_ALL_DIS \
 624                                         | ~((CLK_EN << BIT_PERIL_CLK_AC97)\
 625                                           | (CLK_EN << BIT_PERIL_CLK_SPDIF)\
 626                                           | (CLK_EN << BIT_PERIL_CLK_I2C2)\
 627                                           | (CLK_EN << BIT_PERIL_CLK_SLIMBUS)))
 628 #define CLK_GATE_IP_PERIR_VAL           (CLK_GATE_IP_PERIR_ALL_DIS \
 629                                         | ~((CLK_EN << BIT_PERIR_CLK_KEYIF)))
 630 #define CLK_GATE_BLOCK_VAL              CLK_GATE_BLOCK_ALL_DIS
 631
 632 /* PS_HOLD: Data Hight, Output En */
 633 #define BIT_DAT                         8
 634 #define BIT_EN                          9
 635 #define EXYNOS4_PS_HOLD_CON_VAL         (0x1 << BIT_DAT | 0x1 << BIT_EN)
 636
 637 #endif