board/samsung/smdkv310/mem_setup.S

   1 /*
   2  * Memory setup for SMDKV310 board based on EXYNOS4210
   3  *
   4  * Copyright (C) 2011 Samsung Electronics
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26
  27 #define SET_MIU
  28
  29 #define MEM_DLL
  30
  31 #ifdef CONFIG_CLK_800_330_165
  32 #define DRAM_CLK_330
  33 #endif
  34 #ifdef CONFIG_CLK_1000_200_200
  35 #define DRAM_CLK_200
  36 #endif
  37 #ifdef CONFIG_CLK_1000_330_165
  38 #define DRAM_CLK_330
  39 #endif
  40 #ifdef CONFIG_CLK_1000_400_200
  41 #define DRAM_CLK_400
  42 #endif
  43
  44         .globl mem_ctrl_asm_init
  45 mem_ctrl_asm_init:
  46
  47         /*
  48         * Async bridge configuration at CPU_core:
  49         * 1: half_sync
  50         * 0: full_sync
  51         */
  52         ldr r0, =0x10010350
  53         mov r1, #1
  54         str r1, [r0]
  55
  56 #ifdef SET_MIU
  57         ldr     r0, =EXYNOS4_MIU_BASE   @0x10600000
  58 #ifdef CONFIG_MIU_1BIT_INTERLEAVED
  59         ldr     r1, =0x0000000c
  60         str     r1, [r0, #0x400]        @MIU_INTLV_CONFIG
  61         ldr     r1, =0x40000000
  62         str     r1, [r0, #0x808]        @MIU_INTLV_START_ADDR
  63         ldr     r1, =0xbfffffff
  64         str     r1, [r0, #0x810]        @MIU_INTLV_END_ADDR
  65         ldr     r1, =0x00000001
  66         str     r1, [r0, #0x800]        @MIU_MAPPING_UPDATE
  67 #endif
  68 #ifdef CONFIG_MIU_2BIT_INTERLEAVED
  69         ldr     r1, =0x2000150c
  70         str     r1, [r0, #0x400]        @MIU_INTLV_CONFIG
  71         ldr     r1, =0x40000000
  72         str     r1, [r0, #0x808]        @MIU_INTLV_START_ADDR
  73         ldr     r1, =0xbfffffff
  74         str     r1, [r0, #0x810]        @MIU_INTLV_END_ADDR
  75         ldr     r1, =0x00000001
  76         str     r1, [r0, #0x800]        @MIU_MAPPING_UPDATE
  77 #endif
  78 #ifdef CONFIG_MIU_LINEAR
  79         ldr     r1, =0x40000000
  80         str     r1, [r0, #0x818]        @MIU_SINGLE_MAPPING0_START_ADDR
  81         ldr     r1, =0x7fffffff
  82         str     r1, [r0, #0x820]        @MIU_SINGLE_MAPPING0_END_ADDR
  83         ldr     r1, =0x80000000
  84         str     r1, [r0, #0x828]        @MIU_SINGLE_MAPPING1_START_ADDR
  85         ldr     r1, =0xbfffffff
  86         str     r1, [r0, #0x830]        @MIU_SINGLE_MAPPING1_END_ADDR]
  87         ldr     r1, =0x00000006
  88         str     r1, [r0, #0x800]        @MIU_MAPPING_UPDATE
  89 #endif
  90 #endif
  91         /* DREX0 */
  92         ldr     r0, =EXYNOS4_DMC0_BASE  @0x10400000
  93
  94         ldr     r1, =0xe0000086
  95         str     r1, [r0, #0x1C]         @DMC_PHYCONTROL1
  96
  97         ldr     r1, =0xE3855703
  98         str     r1, [r0, #0x44]         @DMC_PHYZQCONTROL
  99
 100         mov     r2, #0x100000
 101 1:      subs    r2, r2, #1
 102         bne     1b
 103
 104         ldr     r1, =0xe000008e
 105         str     r1, [r0, #0x1C]         @DMC_PHYCONTROL1
 106         ldr     r1, =0xe0000086
 107         str     r1, [r0, #0x1C]         @DMC_PHYCONTROL1
 108
 109         ldr     r1, =0x71101008
 110         str     r1, [r0, #0x18]         @DMC_PHYCONTROL0
 111         ldr     r1, =0x7110100A
 112         str     r1, [r0, #0x18]         @DMC_PHYCONTROL0
 113         ldr     r1, =0xe0000086
 114         str     r1, [r0, #0x1C]         @DMC_PHYCONTROL1
 115         ldr     r1, =0x7110100B
 116         str     r1, [r0, #0x18]         @DMC_PHYCONTROL0
 117
 118         ldr     r1, =0x00000000
 119         str     r1, [r0, #0x20]         @DMC_PHYCONTROL2
 120
 121         ldr     r1, =0x0FFF301a
 122         str     r1, [r0, #0x00]         @DMC_CONCONTROL
 123         ldr     r1, =0x00312640
 124         str     r1, [r0, #0x04]         @DMC_MEMCONTROL]
 125
 126 #ifdef CONFIG_MIU_LINEAR
 127         ldr     r1, =0x40e01323
 128         str     r1, [r0, #0x08]         @DMC_MEMCONFIG0
 129         ldr     r1, =0x60e01323
 130         str     r1, [r0, #0x0C]         @DMC_MEMCONFIG1
 131 #else   /* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
 132         ldr     r1, =0x20e01323
 133         str     r1, [r0, #0x08]         @DMC_MEMCONFIG0
 134         ldr     r1, =0x40e01323
 135         str     r1, [r0, #0x0C]         @DMC_MEMCONFIG1
 136 #endif
 137
 138         ldr     r1, =0xff000000
 139         str     r1, [r0, #0x14]         @DMC_PRECHCONFIG
 140
 141         ldr     r1, =0x000000BC
 142         str     r1, [r0, #0x30]         @DMC_TIMINGAREF
 143
 144 #ifdef DRAM_CLK_330
 145         ldr     r1, =0x3545548d
 146         str     r1, [r0, #0x34]         @DMC_TIMINGROW
 147         ldr     r1, =0x45430506
 148         str     r1, [r0, #0x38]         @DMC_TIMINGDATA
 149         ldr     r1, =0x4439033c
 150         str     r1, [r0, #0x3C]         @DMC_TIMINGPOWER
 151 #endif
 152 #ifdef DRAM_CLK_400
 153         ldr     r1, =0x4046654f
 154         str     r1, [r0, #0x34]         @DMC_TIMINGROW
 155         ldr     r1, =0x56500506
 156         str     r1, [r0, #0x38]         @DMC_TIMINGDATA
 157         ldr     r1, =0x5444033d
 158         str     r1, [r0, #0x3C]         @DMC_TIMINGPOWER
 159 #endif
 160         ldr     r1, =0x07000000
 161         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 162
 163         mov     r2, #0x100000
 164 2:      subs    r2, r2, #1
 165         bne     2b
 166
 167         ldr     r1, =0x00020000
 168         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 169         ldr     r1, =0x00030000
 170         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 171         ldr     r1, =0x00010002
 172         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 173         ldr     r1, =0x00000328
 174         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 175
 176         mov     r2, #0x100000
 177 3:      subs    r2, r2, #1
 178         bne     3b
 179
 180         ldr     r1, =0x0a000000
 181         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 182
 183         mov     r2, #0x100000
 184 4:      subs    r2, r2, #1
 185         bne     4b
 186
 187         ldr     r1, =0x07100000
 188         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 189
 190         mov     r2, #0x100000
 191 5:      subs    r2, r2, #1
 192         bne     5b
 193
 194         ldr     r1, =0x00120000
 195         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 196         ldr     r1, =0x00130000
 197         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 198         ldr     r1, =0x00110002
 199         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 200         ldr     r1, =0x00100328
 201         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 202
 203         mov     r2, #0x100000
 204 6:      subs    r2, r2, #1
 205         bne     6b
 206
 207         ldr     r1, =0x0a100000
 208         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 209
 210         mov     r2, #0x100000
 211 7:      subs    r2, r2, #1
 212         bne     7b
 213
 214         ldr     r1, =0xe000008e
 215         str     r1, [r0, #0x1C]         @DMC_PHYCONTROL1
 216         ldr     r1, =0xe0000086
 217         str     r1, [r0, #0x1C]         @DMC_PHYCONTROL1
 218
 219         mov     r2, #0x100000
 220 8:      subs    r2, r2, #1
 221         bne     8b
 222
 223         /* DREX1 */
 224         ldr     r0, =EXYNOS4_DMC1_BASE  @0x10410000
 225
 226         ldr     r1, =0xe0000086
 227         str     r1, [r0, #0x1C]         @DMC_PHYCONTROL1
 228
 229         ldr     r1, =0xE3855703
 230         str     r1, [r0, #0x44]         @DMC_PHYZQCONTROL
 231
 232         mov     r2, #0x100000
 233 1:      subs    r2, r2, #1
 234         bne     1b
 235
 236         ldr     r1, =0xe000008e
 237         str     r1, [r0, #0x1C]         @DMC_PHYCONTROL1
 238         ldr     r1, =0xe0000086
 239         str     r1, [r0, #0x1C]         @DMC_PHYCONTROL1
 240
 241         ldr     r1, =0x71101008
 242         str     r1, [r0, #0x18]         @DMC_PHYCONTROL0
 243         ldr     r1, =0x7110100A
 244         str     r1, [r0, #0x18]         @DMC_PHYCONTROL0
 245         ldr     r1, =0xe0000086
 246         str     r1, [r0, #0x1C]         @DMC_PHYCONTROL1
 247         ldr     r1, =0x7110100B
 248         str     r1, [r0, #0x18]         @DMC_PHYCONTROL0
 249
 250         ldr     r1, =0x00000000
 251         str     r1, [r0, #0x20]         @DMC_PHYCONTROL2
 252
 253         ldr     r1, =0x0FFF301a
 254         str     r1, [r0, #0x00]         @DMC_CONCONTROL
 255         ldr     r1, =0x00312640
 256         str     r1, [r0, #0x04]         @DMC_MEMCONTROL]
 257
 258 #ifdef CONFIG_MIU_LINEAR
 259         ldr     r1, =0x40e01323
 260         str     r1, [r0, #0x08]         @DMC_MEMCONFIG0
 261         ldr     r1, =0x60e01323
 262         str     r1, [r0, #0x0C]         @DMC_MEMCONFIG1
 263 #else   /* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
 264         ldr     r1, =0x20e01323
 265         str     r1, [r0, #0x08]         @DMC_MEMCONFIG0
 266         ldr     r1, =0x40e01323
 267         str     r1, [r0, #0x0C]         @DMC_MEMCONFIG1
 268 #endif
 269
 270         ldr     r1, =0xff000000
 271         str     r1, [r0, #0x14]         @DMC_PRECHCONFIG
 272
 273         ldr     r1, =0x000000BC
 274         str     r1, [r0, #0x30]         @DMC_TIMINGAREF
 275
 276 #ifdef DRAM_CLK_330
 277         ldr     r1, =0x3545548d
 278         str     r1, [r0, #0x34]         @DMC_TIMINGROW
 279         ldr     r1, =0x45430506
 280         str     r1, [r0, #0x38]         @DMC_TIMINGDATA
 281         ldr     r1, =0x4439033c
 282         str     r1, [r0, #0x3C]         @DMC_TIMINGPOWER
 283 #endif
 284 #ifdef DRAM_CLK_400
 285         ldr     r1, =0x4046654f
 286         str     r1, [r0, #0x34]         @DMC_TIMINGROW
 287         ldr     r1, =0x56500506
 288         str     r1, [r0, #0x38]         @DMC_TIMINGDATA
 289         ldr     r1, =0x5444033d
 290         str     r1, [r0, #0x3C]         @DMC_TIMINGPOWER
 291 #endif
 292
 293         ldr     r1, =0x07000000
 294         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 295
 296         mov     r2, #0x100000
 297 2:      subs    r2, r2, #1
 298         bne     2b
 299
 300         ldr     r1, =0x00020000
 301         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 302         ldr     r1, =0x00030000
 303         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 304         ldr     r1, =0x00010002
 305         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 306         ldr     r1, =0x00000328
 307         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 308
 309         mov     r2, #0x100000
 310 3:      subs    r2, r2, #1
 311         bne     3b
 312
 313         ldr     r1, =0x0a000000
 314         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 315
 316         mov     r2, #0x100000
 317 4:      subs    r2, r2, #1
 318         bne     4b
 319
 320         ldr     r1, =0x07100000
 321         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 322
 323         mov     r2, #0x100000
 324 5:      subs    r2, r2, #1
 325         bne     5b
 326
 327         ldr     r1, =0x00120000
 328         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 329         ldr     r1, =0x00130000
 330         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 331         ldr     r1, =0x00110002
 332         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 333         ldr     r1, =0x00100328
 334         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 335
 336         mov     r2, #0x100000
 337 6:      subs    r2, r2, #1
 338         bne     6b
 339
 340         ldr     r1, =0x0a100000
 341         str     r1, [r0, #0x10]         @DMC_DIRECTCMD
 342
 343         mov     r2, #0x100000
 344 7:      subs    r2, r2, #1
 345         bne     7b
 346
 347         ldr     r1, =0xe000008e
 348         str     r1, [r0, #0x1C]         @DMC_PHYCONTROL1
 349         ldr     r1, =0xe0000086
 350         str     r1, [r0, #0x1C]         @DMC_PHYCONTROL1
 351
 352         mov     r2, #0x100000
 353 8:      subs    r2, r2, #1
 354         bne     8b
 355
 356         /* turn on DREX0, DREX1 */
 357         ldr     r0, =0x10400000         @APB_DMC_0_BASE
 358         ldr     r1, =0x0FFF303a
 359         str     r1, [r0, #0x00]         @DMC_CONCONTROL
 360
 361         ldr     r0, =0x10410000         @APB_DMC_1_BASE
 362         ldr     r1, =0x0FFF303a
 363         str     r1, [r0, #0x00]         @DMC_CONCONTROL
 364
 365         mov     pc, lr