2 * Copyright (C) 2009 Samsung Electronics
3 * Kyungmin Park <kyungmin.park@samsung.com>
4 * Minkyu Kang <mk7.kang@samsung.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/cpu.h>
28 #include <asm/arch/power.h>
43 /* r5 has always zero */
46 ldr r8, =S5PC100_GPIO_BASE
48 /* Disable Watchdog */
49 ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
53 #ifndef CONFIG_ONENAND_IPL
55 ldr r0, =S5PC100_SROMC_BASE
60 /* S5PC100 has 3 groups of interrupt sources */
61 ldr r0, =S5PC100_VIC0_BASE @0xE4000000
62 ldr r1, =S5PC100_VIC1_BASE @0xE4000000
63 ldr r2, =S5PC100_VIC2_BASE @0xE4000000
65 /* Disable all interrupts (VIC0, VIC1 and VIC2) */
67 str r3, [r0, #0x14] @INTENCLEAR
68 str r3, [r1, #0x14] @INTENCLEAR
69 str r3, [r2, #0x14] @INTENCLEAR
71 #ifndef CONFIG_ONENAND_IPL
72 /* Set all interrupts as IRQ */
73 str r5, [r0, #0xc] @INTSELECT
74 str r5, [r1, #0xc] @INTSELECT
75 str r5, [r2, #0xc] @INTSELECT
77 /* Pending Interrupt Clear */
78 str r5, [r0, #0xf00] @INTADDRESS
79 str r5, [r1, #0xf00] @INTADDRESS
80 str r5, [r2, #0xf00] @INTADDRESS
83 #ifndef CONFIG_ONENAND_IPL
91 #ifdef CONFIG_ONENAND_IPL
92 /* init system clock */
97 /* Wakeup support. Don't know if it's going to be used, untested. */
98 ldr r0, =S5PC100_RST_STAT
100 bic r1, r1, #0xfffffff7
109 #ifdef CONFIG_ONENAND_IPL
112 /* Clear wakeup status register */
113 ldr r0, =S5PC100_WAKEUP_STAT
117 /* Load return address and jump to kernel */
118 ldr r0, =S5PC100_INFORM0
120 /* r1 = physical address of s5pc100_cpu_resume function */
123 /* Jump to kernel (sleep.S) */
130 * system_clock_init: Initialize core clock and bus clock.
131 * void system_clock_init(void)
134 ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000
136 /* Set Clock divider */
145 ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
146 str r1, [r8, #0x000] @ APLL_LOCK
147 str r1, [r8, #0x004] @ MPLL_LOCK
148 str r1, [r8, #0x008] @ EPLL_LOCK
149 str r1, [r8, #0x00C] @ HPLL_LOCK
152 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
155 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
158 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
164 /* Set Source Clock */
165 ldr r1, =0x1111 @ A, M, E, HPLL Muxing
166 str r1, [r8, #0x200] @ CLK_SRC0
168 ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing
169 str r1, [r8, #0x204] @ CLK_SRC1
171 ldr r1, =0x9000 @ ARMCLK/4
172 str r1, [r8, #0x400] @ CLK_OUT
174 /* wait at least 200us to stablize all clock */
181 #ifndef CONFIG_ONENAND_IPL
183 * uart_asm_init: Initialize UART's pins
188 str r1, [r0, #0x0] @ GPA0_CON
190 str r1, [r0, #0x20] @ GPA1_CON
195 * tzpc_asm_init: Initialize TZPC