board/samsung/smdk5250/smdk5250.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <fdtdec.h>
  25 #include <asm/io.h>
  26 #include <errno.h>
  27 #include <i2c.h>
  28 #include <lcd.h>
  29 #include <netdev.h>
  30 #include <spi.h>
  31 #include <asm/arch/cpu.h>
  32 #include <asm/arch/gpio.h>
  33 #include <asm/arch/mmc.h>
  34 #include <asm/arch/pinmux.h>
  35 #include <asm/arch/power.h>
  36 #include <asm/arch/sromc.h>
  37 #include <asm/arch/dp_info.h>
  38 #include <power/pmic.h>
  39 #include <power/max77686_pmic.h>
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 #ifdef CONFIG_USB_EHCI_EXYNOS
  44 int board_usb_vbus_init(void)
  45 {
  46         struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
  47                                                 samsung_get_base_gpio_part1();
  48
  49         /* Enable VBUS power switch */
  50         s5p_gpio_direction_output(&gpio1->x2, 6, 1);
  51
  52         /* VBUS turn ON time */
  53         mdelay(3);
  54
  55         return 0;
  56 }
  57 #endif
  58
  59 #ifdef CONFIG_SOUND_MAX98095
  60 static void  board_enable_audio_codec(void)
  61 {
  62         struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
  63                                                 samsung_get_base_gpio_part1();
  64
  65         /* Enable MAX98095 Codec */
  66         s5p_gpio_direction_output(&gpio1->x1, 7, 1);
  67         s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
  68 }
  69 #endif
  70
  71 int board_init(void)
  72 {
  73         gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
  74 #ifdef CONFIG_EXYNOS_SPI
  75         spi_init();
  76 #endif
  77 #ifdef CONFIG_USB_EHCI_EXYNOS
  78         board_usb_vbus_init();
  79 #endif
  80 #ifdef CONFIG_SOUND_MAX98095
  81         board_enable_audio_codec();
  82 #endif
  83         return 0;
  84 }
  85
  86 int dram_init(void)
  87 {
  88         gd->ram_size    = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
  89                         + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
  90                         + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
  91                         + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
  92                         + get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
  93                         + get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
  94                         + get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
  95                         + get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
  96         return 0;
  97 }
  98
  99 #if defined(CONFIG_POWER)
 100 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
 101 {
 102         u32 val;
 103         int ret = 0;
 104
 105         ret = pmic_reg_read(p, reg, &val);
 106         if (ret) {
 107                 debug("%s: PMIC %d register read failed\n", __func__, reg);
 108                 return -1;
 109         }
 110         val |= regval;
 111         ret = pmic_reg_write(p, reg, val);
 112         if (ret) {
 113                 debug("%s: PMIC %d register write failed\n", __func__, reg);
 114                 return -1;
 115         }
 116         return 0;
 117 }
 118
 119 int power_init_board(void)
 120 {
 121         struct pmic *p;
 122
 123         set_ps_hold_ctrl();
 124
 125         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 126
 127         if (pmic_init(I2C_PMIC))
 128                 return -1;
 129
 130         p = pmic_get("MAX77686_PMIC");
 131         if (!p)
 132                 return -ENODEV;
 133
 134         if (pmic_probe(p))
 135                 return -1;
 136
 137         if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
 138                 return -1;
 139
 140         if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
 141                                 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
 142                 return -1;
 143
 144         /* VDD_MIF */
 145         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
 146                                                 MAX77686_BUCK1OUT_1V)) {
 147                 debug("%s: PMIC %d register write failed\n", __func__,
 148                                                 MAX77686_REG_PMIC_BUCK1OUT);
 149                 return -1;
 150         }
 151
 152         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
 153                                                 MAX77686_BUCK1CTRL_EN))
 154                 return -1;
 155
 156         /* VDD_ARM */
 157         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
 158                                         MAX77686_BUCK2DVS1_1_3V)) {
 159                 debug("%s: PMIC %d register write failed\n", __func__,
 160                                                 MAX77686_REG_PMIC_BUCK2DVS1);
 161                 return -1;
 162         }
 163
 164         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
 165                                         MAX77686_BUCK2CTRL_ON))
 166                 return -1;
 167
 168         /* VDD_INT */
 169         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
 170                                         MAX77686_BUCK3DVS1_1_0125V)) {
 171                 debug("%s: PMIC %d register write failed\n", __func__,
 172                                                 MAX77686_REG_PMIC_BUCK3DVS1);
 173                 return -1;
 174         }
 175
 176         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
 177                                         MAX77686_BUCK3CTRL_ON))
 178                 return -1;
 179
 180         /* VDD_G3D */
 181         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
 182                                         MAX77686_BUCK4DVS1_1_2V)) {
 183                 debug("%s: PMIC %d register write failed\n", __func__,
 184                                                 MAX77686_REG_PMIC_BUCK4DVS1);
 185                 return -1;
 186         }
 187
 188         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
 189                                         MAX77686_BUCK3CTRL_ON))
 190                 return -1;
 191
 192         /* VDD_LDO2 */
 193         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
 194                                 MAX77686_LD02CTRL1_1_5V | EN_LDO))
 195                 return -1;
 196
 197         /* VDD_LDO3 */
 198         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
 199                                 MAX77686_LD03CTRL1_1_8V | EN_LDO))
 200                 return -1;
 201
 202         /* VDD_LDO5 */
 203         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
 204                                 MAX77686_LD05CTRL1_1_8V | EN_LDO))
 205                 return -1;
 206
 207         /* VDD_LDO10 */
 208         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
 209                                 MAX77686_LD10CTRL1_1_8V | EN_LDO))
 210                 return -1;
 211
 212         return 0;
 213 }
 214 #endif
 215
 216 void dram_init_banksize(void)
 217 {
 218         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 219         gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
 220                                                         PHYS_SDRAM_1_SIZE);
 221         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 222         gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
 223                                                         PHYS_SDRAM_2_SIZE);
 224         gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
 225         gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
 226                                                         PHYS_SDRAM_3_SIZE);
 227         gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
 228         gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
 229                                                         PHYS_SDRAM_4_SIZE);
 230         gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
 231         gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5,
 232                                                         PHYS_SDRAM_5_SIZE);
 233         gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
 234         gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6,
 235                                                         PHYS_SDRAM_6_SIZE);
 236         gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
 237         gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7,
 238                                                         PHYS_SDRAM_7_SIZE);
 239         gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
 240         gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8,
 241                                                         PHYS_SDRAM_8_SIZE);
 242 }
 243
 244 #ifdef CONFIG_OF_CONTROL
 245 static int decode_sromc(const void *blob, struct fdt_sromc *config)
 246 {
 247         int err;
 248         int node;
 249
 250         node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
 251         if (node < 0) {
 252                 debug("Could not find SROMC node\n");
 253                 return node;
 254         }
 255
 256         config->bank = fdtdec_get_int(blob, node, "bank", 0);
 257         config->width = fdtdec_get_int(blob, node, "width", 2);
 258
 259         err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
 260                         FDT_SROM_TIMING_COUNT);
 261         if (err < 0) {
 262                 debug("Could not decode SROMC configuration\n");
 263                 return -FDT_ERR_NOTFOUND;
 264         }
 265
 266         return 0;
 267 }
 268 #endif
 269
 270 int board_eth_init(bd_t *bis)
 271 {
 272 #ifdef CONFIG_SMC911X
 273         u32 smc_bw_conf, smc_bc_conf;
 274         struct fdt_sromc config;
 275         fdt_addr_t base_addr;
 276         int node;
 277
 278 #ifdef CONFIG_OF_CONTROL
 279         node = decode_sromc(gd->fdt_blob, &config);
 280         if (node < 0) {
 281                 debug("%s: Could not find sromc configuration\n", __func__);
 282                 return 0;
 283         }
 284         node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
 285         if (node < 0) {
 286                 debug("%s: Could not find lan9215 configuration\n", __func__);
 287                 return 0;
 288         }
 289
 290         /* We now have a node, so any problems from now on are errors */
 291         base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
 292         if (base_addr == FDT_ADDR_T_NONE) {
 293                 debug("%s: Could not find lan9215 address\n", __func__);
 294                 return -1;
 295         }
 296 #else
 297         /* Non-FDT configuration - bank number and timing parameters*/
 298         config.bank = CONFIG_ENV_SROM_BANK;
 299         config.width = 2;
 300
 301         config.timing[FDT_SROM_TACS] = 0x01;
 302         config.timing[FDT_SROM_TCOS] = 0x01;
 303         config.timing[FDT_SROM_TACC] = 0x06;
 304         config.timing[FDT_SROM_TCOH] = 0x01;
 305         config.timing[FDT_SROM_TAH] = 0x0C;
 306         config.timing[FDT_SROM_TACP] = 0x09;
 307         config.timing[FDT_SROM_PMC] = 0x01;
 308         base_addr = CONFIG_SMC911X_BASE;
 309 #endif
 310
 311         /* Ethernet needs data bus width of 16 bits */
 312         if (config.width != 2) {
 313                 debug("%s: Unsupported bus width %d\n", __func__,
 314                         config.width);
 315                 return -1;
 316         }
 317         smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
 318                         | SROMC_BYTE_ENABLE(config.bank);
 319
 320         smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |\
 321                         SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
 322                         SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
 323                         SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
 324                         SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |\
 325                         SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
 326                         SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
 327
 328         /* Select and configure the SROMC bank */
 329         exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
 330         s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
 331         return smc911x_initialize(0, base_addr);
 332 #endif
 333         return 0;
 334 }
 335
 336 #ifdef CONFIG_DISPLAY_BOARDINFO
 337 int checkboard(void)
 338 {
 339         printf("\nBoard: SMDK5250\n");
 340
 341         return 0;
 342 }
 343 #endif
 344
 345 #ifdef CONFIG_GENERIC_MMC
 346 int board_mmc_init(bd_t *bis)
 347 {
 348         int err;
 349
 350         err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
 351         if (err) {
 352                 debug("SDMMC0 not configured\n");
 353                 return err;
 354         }
 355
 356         err = s5p_mmc_init(0, 8);
 357         return err;
 358 }
 359 #endif
 360
 361 static int board_uart_init(void)
 362 {
 363         int err;
 364
 365         err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
 366         if (err) {
 367                 debug("UART0 not configured\n");
 368                 return err;
 369         }
 370
 371         err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
 372         if (err) {
 373                 debug("UART1 not configured\n");
 374                 return err;
 375         }
 376
 377         err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
 378         if (err) {
 379                 debug("UART2 not configured\n");
 380                 return err;
 381         }
 382
 383         err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
 384         if (err) {
 385                 debug("UART3 not configured\n");
 386                 return err;
 387         }
 388
 389         return 0;
 390 }
 391
 392 #ifdef CONFIG_BOARD_EARLY_INIT_F
 393 int board_early_init_f(void)
 394 {
 395         int err;
 396         err = board_uart_init();
 397         if (err) {
 398                 debug("UART init failed\n");
 399                 return err;
 400         }
 401 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 402         board_i2c_init(gd->fdt_blob);
 403 #endif
 404         return err;
 405 }
 406 #endif
 407
 408 #ifdef CONFIG_LCD
 409 void cfg_lcd_gpio(void)
 410 {
 411         struct exynos5_gpio_part1 *gpio1 =
 412                 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 413
 414         /* For Backlight */
 415         s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
 416         s5p_gpio_set_value(&gpio1->b2, 0, 1);
 417
 418         /* LCD power on */
 419         s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
 420         s5p_gpio_set_value(&gpio1->x1, 5, 1);
 421
 422         /* Set Hotplug detect for DP */
 423         s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
 424 }
 425
 426 vidinfo_t panel_info = {
 427         .vl_freq        = 60,
 428         .vl_col         = 2560,
 429         .vl_row         = 1600,
 430         .vl_width       = 2560,
 431         .vl_height      = 1600,
 432         .vl_clkp        = CONFIG_SYS_LOW,
 433         .vl_hsp         = CONFIG_SYS_LOW,
 434         .vl_vsp         = CONFIG_SYS_LOW,
 435         .vl_dp          = CONFIG_SYS_LOW,
 436         .vl_bpix        = 4,    /* LCD_BPP = 2^4, for output conosle on LCD */
 437
 438         /* wDP panel timing infomation */
 439         .vl_hspw        = 32,
 440         .vl_hbpd        = 80,
 441         .vl_hfpd        = 48,
 442
 443         .vl_vspw        = 6,
 444         .vl_vbpd        = 37,
 445         .vl_vfpd        = 3,
 446         .vl_cmd_allow_len = 0xf,
 447
 448         .win_id         = 3,
 449         .cfg_gpio       = cfg_lcd_gpio,
 450         .backlight_on   = NULL,
 451         .lcd_power_on   = NULL,
 452         .reset_lcd      = NULL,
 453         .dual_lcd_enabled = 0,
 454
 455         .init_delay     = 0,
 456         .power_on_delay = 0,
 457         .reset_delay    = 0,
 458         .interface_mode = FIMD_RGB_INTERFACE,
 459         .dp_enabled     = 1,
 460 };
 461
 462 static struct edp_device_info edp_info = {
 463         .disp_info = {
 464                 .h_res = 2560,
 465                 .h_sync_width = 32,
 466                 .h_back_porch = 80,
 467                 .h_front_porch = 48,
 468                 .v_res = 1600,
 469                 .v_sync_width  = 6,
 470                 .v_back_porch = 37,
 471                 .v_front_porch = 3,
 472                 .v_sync_rate = 60,
 473         },
 474         .lt_info = {
 475                 .lt_status = DP_LT_NONE,
 476         },
 477         .video_info = {
 478                 .master_mode = 0,
 479                 .bist_mode = DP_DISABLE,
 480                 .bist_pattern = NO_PATTERN,
 481                 .h_sync_polarity = 0,
 482                 .v_sync_polarity = 0,
 483                 .interlaced = 0,
 484                 .color_space = COLOR_RGB,
 485                 .dynamic_range = VESA,
 486                 .ycbcr_coeff = COLOR_YCBCR601,
 487                 .color_depth = COLOR_8,
 488         },
 489 };
 490
 491 static struct exynos_dp_platform_data dp_platform_data = {
 492         .phy_enable     = set_dp_phy_ctrl,
 493         .edp_dev_info   = &edp_info,
 494 };
 495
 496 void init_panel_info(vidinfo_t *vid)
 497 {
 498         vid->rgb_mode   = MODE_RGB_P,
 499
 500         exynos_set_dp_platform_data(&dp_platform_data);
 501 }
 502 #endif