2 * Copyright (C) 2012 Samsung Electronics
4 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/dwmmc.h>
17 #include <asm/arch/gpio.h>
18 #include <asm/arch/mmc.h>
19 #include <asm/arch/pinmux.h>
20 #include <asm/arch/power.h>
21 #include <asm/arch/sromc.h>
22 #include <power/pmic.h>
23 #include <power/max77686_pmic.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #if defined CONFIG_EXYNOS_TMU
30 * Boot Time Thermal Analysis for SoC temperature threshold breach
32 static void boot_temp_check(void)
36 switch (tmu_monitor(&temp)) {
37 /* Status TRIPPED ans WARNING means corresponding threshold breach */
38 case TMU_STATUS_TRIPPED:
39 puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
43 case TMU_STATUS_WARNING:
44 puts("EXYNOS_TMU: WARNING! Temperature very high\n");
47 * TMU_STATUS_INIT means something is wrong with temperature sensing
48 * and TMU status was changed back from NORMAL to INIT.
52 debug("EXYNOS_TMU: Unknown TMU state\n");
58 struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */
59 int cros_ec_err; /* Error for cros_ec, 0 if ok */
62 static struct local_info local;
64 #ifdef CONFIG_SOUND_MAX98095
65 static void board_enable_audio_codec(void)
67 struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
68 samsung_get_base_gpio_part1();
70 /* Enable MAX98095 Codec */
71 s5p_gpio_direction_output(&gpio1->x1, 7, 1);
72 s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
76 struct cros_ec_dev *board_get_cros_ec_dev(void)
78 return local.cros_ec_dev;
81 static int board_init_cros_ec_devices(const void *blob)
83 local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
84 if (local.cros_ec_err)
85 return -1; /* Will report in board_late_init() */
92 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
94 #if defined CONFIG_EXYNOS_TMU
95 if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
96 debug("%s: Failed to init TMU\n", __func__);
102 #ifdef CONFIG_EXYNOS_SPI
106 if (board_init_cros_ec_devices(gd->fdt_blob))
109 #ifdef CONFIG_SOUND_MAX98095
110 board_enable_audio_codec();
120 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
121 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
122 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
127 #if defined(CONFIG_POWER)
128 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
133 ret = pmic_reg_read(p, reg, &val);
135 debug("%s: PMIC %d register read failed\n", __func__, reg);
139 ret = pmic_reg_write(p, reg, val);
141 debug("%s: PMIC %d register write failed\n", __func__, reg);
147 int power_init_board(void)
153 if (pmic_init(I2C_PMIC))
156 p = pmic_get("MAX77686_PMIC");
163 if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
166 if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
167 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
171 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
172 MAX77686_BUCK1OUT_1V)) {
173 debug("%s: PMIC %d register write failed\n", __func__,
174 MAX77686_REG_PMIC_BUCK1OUT);
178 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
179 MAX77686_BUCK1CTRL_EN))
183 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
184 MAX77686_BUCK2DVS1_1_3V)) {
185 debug("%s: PMIC %d register write failed\n", __func__,
186 MAX77686_REG_PMIC_BUCK2DVS1);
190 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
191 MAX77686_BUCK2CTRL_ON))
195 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
196 MAX77686_BUCK3DVS1_1_0125V)) {
197 debug("%s: PMIC %d register write failed\n", __func__,
198 MAX77686_REG_PMIC_BUCK3DVS1);
202 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
203 MAX77686_BUCK3CTRL_ON))
207 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
208 MAX77686_BUCK4DVS1_1_2V)) {
209 debug("%s: PMIC %d register write failed\n", __func__,
210 MAX77686_REG_PMIC_BUCK4DVS1);
214 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
215 MAX77686_BUCK3CTRL_ON))
219 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
220 MAX77686_LD02CTRL1_1_5V | EN_LDO))
224 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
225 MAX77686_LD03CTRL1_1_8V | EN_LDO))
229 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
230 MAX77686_LD05CTRL1_1_8V | EN_LDO))
234 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
235 MAX77686_LD10CTRL1_1_8V | EN_LDO))
242 void dram_init_banksize(void)
247 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
248 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
249 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
251 gd->bd->bi_dram[i].start = addr;
252 gd->bd->bi_dram[i].size = size;
256 static int decode_sromc(const void *blob, struct fdt_sromc *config)
261 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
263 debug("Could not find SROMC node\n");
267 config->bank = fdtdec_get_int(blob, node, "bank", 0);
268 config->width = fdtdec_get_int(blob, node, "width", 2);
270 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
271 FDT_SROM_TIMING_COUNT);
273 debug("Could not decode SROMC configuration Error: %s\n",
275 return -FDT_ERR_NOTFOUND;
280 int board_eth_init(bd_t *bis)
282 #ifdef CONFIG_SMC911X
283 u32 smc_bw_conf, smc_bc_conf;
284 struct fdt_sromc config;
285 fdt_addr_t base_addr;
288 node = decode_sromc(gd->fdt_blob, &config);
290 debug("%s: Could not find sromc configuration\n", __func__);
293 node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
295 debug("%s: Could not find lan9215 configuration\n", __func__);
299 /* We now have a node, so any problems from now on are errors */
300 base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
301 if (base_addr == FDT_ADDR_T_NONE) {
302 debug("%s: Could not find lan9215 address\n", __func__);
306 /* Ethernet needs data bus width of 16 bits */
307 if (config.width != 2) {
308 debug("%s: Unsupported bus width %d\n", __func__,
312 smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
313 | SROMC_BYTE_ENABLE(config.bank);
315 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |
316 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
317 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
318 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
319 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |
320 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
321 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
323 /* Select and configure the SROMC bank */
324 exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
325 s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
326 return smc911x_initialize(0, base_addr);
331 #ifdef CONFIG_DISPLAY_BOARDINFO
334 const char *board_name;
336 board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
337 if (board_name == NULL)
338 printf("\nUnknown Board\n");
340 printf("\nBoard: %s\n", board_name);
346 #ifdef CONFIG_GENERIC_MMC
347 int board_mmc_init(bd_t *bis)
350 /* dwmmc initializattion for available channels */
351 ret = exynos_dwmmc_init(gd->fdt_blob);
353 debug("dwmmc init failed\n");
359 static int board_uart_init(void)
361 int err, uart_id, ret = 0;
363 for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
364 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
366 debug("UART%d not configured\n",
367 (uart_id - PERIPH_ID_UART0));
374 #ifdef CONFIG_BOARD_EARLY_INIT_F
375 int board_early_init_f(void)
378 err = board_uart_init();
380 debug("UART init failed\n");
383 #ifdef CONFIG_SYS_I2C_INIT_BOARD
384 board_i2c_init(gd->fdt_blob);
391 void exynos_cfg_lcd_gpio(void)
393 struct exynos5_gpio_part1 *gpio1 =
394 (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
397 s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
398 s5p_gpio_set_value(&gpio1->b2, 0, 1);
401 s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
402 s5p_gpio_set_value(&gpio1->x1, 5, 1);
404 /* Set Hotplug detect for DP */
405 s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
408 void exynos_set_dp_phy(unsigned int onoff)
410 set_dp_phy_ctrl(onoff);
414 #ifdef CONFIG_BOARD_LATE_INIT
415 int board_late_init(void)
417 stdio_print_current_devices();
419 if (local.cros_ec_err) {
420 /* Force console on */
421 gd->flags &= ~GD_FLG_SILENT;
423 printf("cros-ec communications failure %d\n",
425 puts("\nPlease reset with Power+Refresh\n\n");
426 panic("Cannot init cros-ec device");